CY7C63221A-PXC Cypress Semiconductor Corp, CY7C63221A-PXC Datasheet - Page 13

• Manufacturer Part Number: CY7C63221A-PXC
• Description: IC MCU 3K USB LS PERIPH 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63221A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 8
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1861; CY7C63221A-PXC

8.3
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into
the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X
to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that
specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.
Note: All bits of all registers are cleared to all zeros on reset, except the Processor Status and Control Register (Figure 18-
1). All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always be
written as 0 and be treated as undefined by reads.
Table 8-1. I/O Register Summary
Document #: 38-08028 Rev. *B
Port 0 Data
Port 1 Data
Port 2 Data
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 0 Interrupt Polarity
Port 1 Interrupt Polarity
Port 0 Mode0
Port 0 Mode1
Port 1 Mode0
Port 1 Mode1
USB Device Address
EP0 Counter Register
EP0 Mode Register
EP1 Counter Register
EP1 Mode Register
USB Status & Control
Global Interrupt Enable
Endpoint Interrupt Enable
Timer (LSB)
Timer (MSB)
WDR Clear
Clock Configuration
Processor Status & Control
Register Name
I/O Register Summary
I/O Address
0x0A
0x0B
0x0C
0x0D
0xFF
0x00
0x01
0x02
0x04
0x05
0x06
0x07
0x10
0x12
0x13
0x14
0x1F
0x20
0x21
0x24
0x25
0x26
0xF8
0x11
FOR
FOR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
W
W
R
R
R
GPIO Port 0
GPIO Port 1
Auxiliary input register for D+, D–, VREG, XTALIN,
XTALOUT
Interrupt enable for pins in Port 0
Interrupt enable for pins in Port 1
Interrupt polarity for pins in Port 0
Interrupt polarity for pins in Port 1
Controls output configuration for Port 0
Controls output configuration for Port 1
USB Device Address register
USB Endpoint 0 counter register
USB Endpoint 0 configuration register
USB Endpoint 1 counter register
USB Endpoint 1 configuration register
USB status and control register
Global interrupt enable register
USB endpoint interrupt enables
Lower 8 bits of free-running timer (1 MHz)
Upper 4 bits of free-running timer
Watch Dog Reset clear
Internal / External Clock configuration register
Processor status and control
Function
CY7C63221/31A
enCoRe™ USB
Page 13 of 50
12-2
12-3
12-8
19-4
19-5
19-6
19-7
12-4
12-5
12-6
12-7
14-1
14-4
14-2
14-4
14-3
13-1
19-1
19-2
17-1
17-2
18-1
Fig.
9-2
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