CY7C63221A-PXC Cypress Semiconductor Corp, CY7C63221A-PXC Datasheet - Page 30

• Manufacturer Part Number: CY7C63221A-PXC
• Description: IC MCU 3K USB LS PERIPH 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63221A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 8
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1861; CY7C63221A-PXC

Bit 6: Watchdog Reset
Bit 5: Bus Interrupt Event
Bit 4: LVR/BOR Reset
Bit 3: Suspend
Bit 2: Interrupt Enable Sense
Bit 1: Reserved. Must be written as a 0.
Bit 0: Run
During power-up, or during a low-voltage reset, the Processor Status and Control Register is set to 00010001, which indicates a
LVR/BOR (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). Note that during the t
start-up (explained in Section 10.1), a Watchdog Reset will also occur. When a WDR occurs during the power-up suspend interval,
firmware would read 01010001 from the Status and Control Register after power-up. Normally the LVR/BOR bit should be cleared
so that a subsequent WDR can be clearly identified. Note that if a USB bus reset (long SE0) is received before firmware examines
this register, the Bus Interrupt Event bit would also be set.
Document #: 38-08028 Rev. *B
1 = There are pending interrupts.
0 = No pending interrupts.
The Watchdog Timer Reset (WDR) occurs when the internal Watchdog timer rolls over. The timer will roll over and WDR will
occur if it is not cleared within t
a watchdog reset can occur with a POR/LVR/BOR event, as discussed at the end of this section.
1 = A watchdog reset occurs.
0 = No watchdog reset.
The Bus Reset Status is set whenever the event for the USB Bus Reset or PS/2 Activity interrupt occurs. The event type (USB
or PS/2) is selected by the state of the USB-PS/2 Interrupt Mode bit in the USB Status and Control Register (see Figure 13-
1). The details on the event conditions that set this bit are given in Section 19.3. In either mode, this bit is set as soon as the
event has lasted for 128–256 µs, and the bit will be set even if the interrupt is not enabled. The bit is only cleared by firmware
or LVR/WDR.
1 = A USB reset occurred or PS/2 Activity is detected, depending on USB-PS/2 Interrupt Select bit.
0 = No event detected since last cleared by firmware or LVR/WDR.
The Low-voltage or Brown-out Reset is set to ‘1’ during a power-on reset. Firmware can check bits 4 and 6 in the reset handler
to determine whether a reset was caused by a LVR/BOR condition or a watchdog timeout. This bit is not affected by WDR.
Note that a LVR/BOR event may be followed by a watchdog reset before firmware begins executing, as explained at the end
of this section.
1 = A POR or LVR has occurred.
0 = No POR nor LVR since this pit last cleared.
Writing a '1' to the Suspend bit will halt the processor and cause the microcontroller to enter the suspend mode that significantly
reduces power consumption. An interrupt or USB bus activity will cause the device to come out of suspend. After coming out
of suspend, the device will resume firmware execution at the instruction following the IOWR that put the part into suspend.
When writing the suspend bit with a resume condition present (such as non-idle USB activity), the suspend state will still be
entered, followed immediately by the wake-up process (with appropriate delays for the clock start-up). See Section 11.0 for
more details on suspend mode operation.
1 = Suspend the processor.
0 = Not in suspend mode. Cleared by the hardware when resuming from suspend.
This bit shows whether interrupts are enabled or disabled. Firmware has no direct control over this bit as writing a zero or one
to this bit position will have no effect on interrupts. This bit is further gated with the bit settings of the Global Interrupt Enable
Register (Figure 19-1) and USB Endpoint Interrupt Enable Register (Figure 19-2). Instructions DI, EI, and RETI manipulate
the state of this bit.
1 = Interrupts are enabled.
0 = Interrupts are masked off.
This bit is manipulated by the HALT instruction. When Halt is executed, the processor clears the run bit and halts at the end
of the current instruction. The processor remains halted until a reset occurs (low-voltage, brown-out, or watchdog). This bit
should normally be written as a ‘1’.
WATCH
FOR
FOR
(see Section 24.0 for the value of t
WATCH
). This bit is cleared by an LVR/BOR. Note that
CY7C63221/31A
enCoRe™ USB
START
ms partial suspend at
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