CY7C63221A-PXC Cypress Semiconductor Corp, CY7C63221A-PXC Datasheet - Page 32

• Manufacturer Part Number: CY7C63221A-PXC
• Description: IC MCU 3K USB LS PERIPH 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63221A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 8
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1861; CY7C63221A-PXC

19.2
Interrupt latency can be calculated from the following equation:
Interrupt Latency = (Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +
For example, if a 5-clock-cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine will execute a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt
is issued. With a 6 MHz external resonator, internal CPU clock speed is 12 MHz, so 20 clocks take 20/12 MHz = 1.67 µs.
19.3
The following sections provide details on the different types of interrupt sources.
Bit 7: Wake-up Interrupt Enable
Bit 6: GPIO Interrupt Enable
Bit [5:3]: Reserved
Bit 2: 1.024-ms Interrupt Enable
Document #: 38-08028 Rev. *B
Read/Write
Bit Name
The internal wake-up timer is normally used to wake the part from suspend mode, but it can also provide an interrupt when
the part is awake. The wake-up timer is cleared whenever the Wake-up Interrupt Enable bit is written to a 0, and runs whenever
that bit is written to a 1. When the interrupt is enabled, the wake-up timer provides periodic interrupts at multiples of period,
as described in Section 11.2.
1 = Enable wake-up timer for periodic wake-up.
0 = Disable and power-off wake-up timer.
Each GPIO pin can serve as an interrupt input. During a reset, GPIO interrupts are disabled by clearing all GPIO interrupt
enable registers. Writing a ‘1’ to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin. These
registers are shown in Figure 19-4 for Port 0 and Figure 19-5 for Port 1. In addition to enabling the desired individual pins for
interrupt, the main GPIO interrupt must be enabled, as explained in Section 19.0.
The polarity that triggers an interrupt is controlled independently for each GPIO pin by the GPIO Interrupt Polarity Registers.
Setting a Polarity bit to ‘0’ allows an interrupt on a falling GPIO edge, while setting a Polarity bit to ‘1’ allows an interrupt on a
rising GPIO edge. The Polarity Registers reset to 0 and are shown in Figure 19-6 for Port 0 and Figure 19-7 for Port 1.
All of the GPIO pins share a single interrupt vector, which means the firmware will need to read the GPIO ports with enabled
interrupts to determine which pin or pins caused an interrupt.The GPIO interrupt structure is illustrated in Figure 19-8.
Note that if one port pin triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned
to its inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. The CY7C63221/31A does not assign
interrupt priority to different port pins and the Port Interrupt Enable Registers are not affected by the interrupt acknowledge
process.
1 = Enable
0 = Disable
The 1.024-ms interrupts are periodic timer interrupts from the free-running timer (based on the 6-MHz clock). The user should
disable this interrupt before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts
(128-µs interrupt and 1.024-ms interrupt) first or the suspend request first when waking up.
1 = Enable. Periodic interrupts will be generated approximately every 1.024 ms.
0 = Disable.
Reset
Bit #
Interrupt Latency
Interrupt Sources
Wake-up
Interrupt
Enable
R/W
7
0
(5 clock cycles for the JMP instruction)
Interrupt
Figure 19-1. Global Interrupt Enable Register (Address 0x20)
Enable
GPIO
R/W
6
0
FOR
FOR
5
0
-
Reserved
4
0
-
3
0
-
1.024-ms
Interrupt
Enable
R/W
2
0
CY7C63221/31A
enCoRe™ USB
Interrupt
128-µs
Enable
R/W
1
0
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PS/2 Activity
Intr. Enable
USB Bus
Reset /
R/W
0
0
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