CY7C63221A-PXC Cypress Semiconductor Corp, CY7C63221A-PXC Datasheet - Page 21

• Manufacturer Part Number: CY7C63221A-PXC
• Description: IC MCU 3K USB LS PERIPH 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63221A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 8
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1861; CY7C63221A-PXC

Bit [7:2]: Reserved
Bit [1:0]: P1[1:0] Mode 1
Each pin can be independently configured as high-impedance inputs, inputs with internal pull-ups, open drain outputs, or tradi-
tional CMOS outputs with selectable drive strengths.
The driving state of each GPIO pin is determined by the value written to the pin’s Data Register and by its associated Mode0 and
Mode1 bits. Table 12-1 lists the configuration states based on these bits. The GPIO ports default on reset to all Data and Mode
Registers cleared, so the pins are all in a high-impedance state. The available GPIO output drive strength are:
Note that open drain mode can be achieved by fixing the Data and Mode1 Registers LOW, and switching the Mode0 register.
Input thresholds are CMOS, or TTL as shown in the table (See Section 23.0 for the input threshold voltage in TTL or CMOS
modes). Both input modes include hysteresis to minimize noise sensitivity. In suspend mode, if a pin is used for a wake-up
interrupt using an external R-C circuit, CMOS mode is preferred for lowest power.
Table 12-1. Ports 0 and 1 Output Control Truth Table
12.1
Port 2 serves as an auxiliary input port as shown in Figure 12-8. The Port 2 inputs all have TTL input thresholds.
Document #: 38-08028 Rev. *B
Read/Write
• Hi-Z Mode (Mode1 = 0 and Mode0 = 0)
• Low Sink Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data Register = 0)
• Medium Sink Mode (Mode1 = 0, Mode0 = 1, and the pin’s Data Register = 0)
• High Sink Mode (Mode1 = 1, Mode0 = 1, and the pin’s Data Register = 0)
• High Drive Mode (Mode1 = 0 or 1, Mode0 = 1, and the pin’s Data Register = 1)
• Resistive Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data Register = 1)
Bit Name
Data Register
1 = Port Pin Mode 1 is logic HIGH
0 = Port Pin Mode 1 is logic LOW
Q1, Q2, and Q3 (Figure 12-1) are OFF. The GPIO pin is not driven internally. Performing a read from the Port Data Register
return the actual logic value on the port pins.
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of sinking 2 mA of current.
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of sinking 8 mA of current.
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of sinking 50 mA of current.
Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is capable of sourcing 2 mA of current.
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with an internal 14-kΩ resistor.
Reset
Bit #
Auxiliary Input Port
0
1
0
1
0
1
0
1
7
0
-
Mode1
0
0
1
1
Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D)
6
0
-
FOR
FOR
Mode0
5
0
-
0
1
0
1
Reserved
4
0
-
Output Drive Strength
Medium (8 mA) Sink
High (50 mA) Sink
Low (2 mA) Sink
High Drive
High Drive
Resistive
3
0
-
Hi-Z
Hi-Z
2
0
-
CY7C63221/31A
enCoRe™ USB
Input Threshold
W
1
0
P1[1:0] Mode1
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
TTL
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