20-668-0011 Rabbit Semiconductor, 20-668-0011 Datasheet - Page 156

• Manufacturer Part Number: 20-668-0011
• Description: IC MPU RABIT3000A 55.5MHZ128LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 20-668-0011

• Processor Type: Rabbit 3000 8-Bit
• Speed: 55.5MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 55.5 MHz
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Number Of Programmable I/os: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 316-1061

Several types of data encoding are available in the HDLC mode. In addition to the normal
NRZ, they are NRZI, biphase-level (Manchester), biphase-space (FM0), and biphase-
mark (FM1). Examples of these encodings are shown below. Note that the signal level
does not convey information in NRZI, biphase-space, and biphase-mark. Instead it is the
placement of the transitions that determine the data. In biphase-level it is the polarity of
the transition that determines the data.
Figure 18-1. Examples of Data Encoding In the HDLC Mode
In the HDLC mode the internal clock comes from the output of Timer A2/Timer A3. The
timer output is divided by 16 to form the transmit clock, and is fed to the digital phase-
locked loop (DPLL) to form the receive clock. The DPLL is basically just a divide-by-16
counter that uses the timing of the transitions on the receive data stream to adjust its count.
The DPLL adjusts the count so that the DPLL output will be properly placed in the bit
cells to sample the receive data. To work properly, then, transitions are required in the
receive data stream. NRZ data encoding does not guarantee transitions in all cases (a long
string of zeros, for example), but the other data encodings do. NRZI guarantees transitions
because of the inserted zeros, and the biphase encodings all have at least one transition per
bit cell.
The DPLL counter normally counts by 16, but if a transition occurs earlier or later than
expected, the count will be modified during the next count cycle. If the transition occurs
earlier than expected, it means that the bit cell boundaries are early with respect to the
DPLL-tracked bit-cell boundaries, so the count is shortened by either one or two counts. If
the transition occurs later than expected, it means that the bit-cell boundaries are late with
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Rabbit 3000 Microprocessor User’s Manual