20-668-0011 Rabbit Semiconductor, 20-668-0011 Datasheet - Page 159

• Manufacturer Part Number: 20-668-0011
• Description: IC MPU RABIT3000A 55.5MHZ128LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 20-668-0011

• Processor Type: Rabbit 3000 8-Bit
• Speed: 55.5MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 55.5 MHz
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Number Of Programmable I/os: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 316-1061

Biphase-mark encoding and biphase-space encoding are identical as far as the DPLL is
concerned, and are similar to biphase-level encoding. The primary difference is the place-
ment of the clock and data transitions. With these encodings the clock transitions are at the
bit-cell boundary, the data transitions are at the center of the bit cell, and the DPLL opera-
tion is adjusted accordingly. Decoding biphase-mark or biphase-space encoding requires
that the data be sampled by both edges of the recovered receive clock.
18.4 Register Descriptions
Chapter 18 Serial Ports E – F
Bit(s)
Bit(s)
Bit(s)
7:0
7:0
7:0
Serial Port x Long Stop Register
Serial Port x Address Register
Serial Port x Data Register
Value
Value
Value
Write
Write
Write
Read
Read
Read
Returns the contents of the receive buffer.
Loads the transmit buffer with a data byte for transmission.
Returns the contents of the receive buffer.
Loads the transmit buffer with an address byte, marked with a “zero” address bit,
for transmission. In the HDLC mode, the last byte of a frame must be written to
this register to enable subsequent CRC and closing flag transmission.
Returns the contents of the receive buffer.
Loads the transmit buffer with an address byte, marked with a “one” address bit,
for transmission. In the HDLC mode, the last byte of a frame is written to this
register to enable subsequent closing flag transmission.
(SEDR)
(SFDR)
(SEAR)
(SFAR)
(SELR)
(SFLR)
Description
Description
Description
(Address = 0x00CA)
(Address = 0x00DA)
(Address = 0x00C8)
(Address = 0x00D8)
(Address = 0x00C9)
(Address = 0x00D9)
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