MPC866PZP133A Freescale Semiconductor, MPC866PZP133A Datasheet - Page 74

• Manufacturer Part Number: MPC866PZP133A
• Description: IC MPU POWERQUICC 133MHZ 357PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICCr

Specifications of MPC866PZP133A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 133MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 133 MHz
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Core Size: 32 Bit
• Program Memory Size: 24KB
• Cpu Speed: 133MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 357
• Supply Voltage Range: 1.7V To 1.9V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FEC Electrical Characteristics
Figure 73
14 FEC Electrical Characteristics
This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing
specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII
signals use TTL signal levels compatible with devices operating at either 5.0 or 3.3 V.
14.1 MII Receive Signal Timing (MII_RXD [3:0], MII_RX_DV,
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum
frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%.
Table 33
Figure 74
74
UtpClk
PHSELn
TxClav
TxEnb
UTPB
SOC
Num
M1
M2
M3
M4
MII_RX_ER, MII_RX_CLK)
shows the timings for MII receive signal.
shows signal timings during UTOPIA transmit operations.
shows the timings for MII receive signal.
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
MII_RX_CLK pulse width high
MII_RX_CLK pulse width low
U2
5
HighZ at MPHY
MPC866/MPC859 Hardware Specifications, Rev. 2
Characteristic
Table 33. MII Receive Signal Timing
Figure 73. UTOPIA Transmit Timing
U2
2
U2
5
U3
U1
3
1
35%
35%
Min
U4
5
5
4
65%
65%
Max
—
—
U1
MII_RX_CLK period
MII_RX_CLK period
Freescale Semiconductor
High-Z at MPHY
Unit
ns
ns