MPC8541ECVTALF Freescale Semiconductor, MPC8541ECVTALF Datasheet - Page 31

• Manufacturer Part Number: MPC8541ECVTALF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8541ECVTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8.3.2
Table 28
Freescale Semiconductor
At recommended operating conditions with LV
Input high current
Input low current
Note:
1. Note that the symbol V
MDC frequency
MDC period
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. This parameter is dependent on the system clock speed (that is, for a system clock of 267 MHz, the delay is 70 ns and for
3. This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a
4. Guaranteed by design.
(reference)(state)
symbolizes management data timing (MD) for the time t
invalid (X) or data hold time. Also, t
signals (D) reach the valid state (V) relative to the t
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
a system clock of 333 MHz, the delay is 58 ns).
CCB clock of 333 MHz, the delay is 48 ns).
Parameter/Condition
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Parameter
provides the MII management AC timing specifications.
MII Management AC Electrical Specifications
for inputs and t
Table 27. MII Management DC Electrical Characteristics (continued)
IN
, in this case, represents the OV
Table 28. MII Management AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
Symbol
I
I
IH
IL
MDDVKH
DD
Symbol
t
t
t
t
MDKHDX
MDDXKH
MDKHDV
MDDVKH
t
t
t
MDCH
MDCR
is 3.3 V ± 5%.
f
t
MDHF
MDC
MDC
LV
LV
symbolizes management data timing (MD) with respect to the time data input
DD
DD
1
= Max
= Max
MDC
Conditions
0.893
Min
MDC
clock reference (K) going to the high (H) state or setup time. For
96
32
10
IN
—
—
5
0
symbol referenced in
V
from clock reference (K) high (H) until data outputs (D) are
V
IN
IN
1
= 0.5 V
= 2.1 V
Typ
(first two letters of functional block)(signal)(state)
—
—
—
—
—
—
—
—
Table 1
–600
2*[1/(f
2*[1/(f
Min
for outputs. For example, t
—
Ethernet: Three-Speed, MII Management
1120
Max
10.4
and
ccb_clk
ccb_clk
10
10
—
—
—
Table
/8)]
/8)]
2.
Max
40
—
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
MDKHDX
Notes
Unit
μA
μA
2
3
3
31