MPC8541ECVTALF Freescale Semiconductor, MPC8541ECVTALF Datasheet - Page 76

• Manufacturer Part Number: MPC8541ECVTALF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8541ECVTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

System Design Information
17 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8541E.
17.1
The MPC8541E includes five PLLs.
17.2
Each of the PLLs listed above is provided with power through independent power supply pins (AV
AV
and preferably these voltages are derived directly from V
as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias.
76
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1. The platform PLL (AV
2. The e500 Core PLL (AV
3. The CPM PLL (AV
4. The PCI1 PLL (AV
5. The PCI2 PLL (AV
2, AV
input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL
ratio configuration bits as described in
frequency ratio between the e500 core clock and the platform clock is selected using the e500
PLL ratio configuration bits as described in
internally by the CPM block. The ratio between the CPM PLL and the platform clock is fixed and
not under user control.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
System Clocking
PLL Power Supply Filtering
DD
3, AV
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4, and AV
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DD
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4) generates the clocking for the first PCI bus.
5) generates the clock for the second PCI bus.
3) is slaved to the platform clock and is used to generate clocks used
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DD
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1
)
2
generates the platform clock from the externally supplied SYSCLK
5 respectively). The AV
)
generates the core clock as a slave to the platform clock. The
Section 15.2, “Platform/System PLL
Section 15.3, “e500 Core PLL
Figure
DD
DD
through a low frequency filter scheme such
49, one to each of the five AV
level should always be equivalent to V
DD
pin being supplied to minimize
Ratio.”
Ratio.”
Freescale Semiconductor
DD
pins. By
DD
DD
1,
DD
,