MPC8541EVTAPF Freescale Semiconductor, MPC8541EVTAPF Datasheet - Page 83

• Manufacturer Part Number: MPC8541EVTAPF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIIr

Specifications of MPC8541EVTAPF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 833MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 1.14V To 1.26V
• Rohs Compliant: Yes
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 833MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

18 Document Revision History
Table 51
Freescale Semiconductor
Rev. No.
4.2
4.1
3.2
3.1
4
3
2
1
0
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides a revision history for this hardware specification.
8/29/2005
07/2007
12/2006
11/2006
10/2005
1/2008
8/2005
6/2005
6/2005
Date
Added “Note: Rise/Fall Time on CPM Input Pins” and following note text to
Timing
Inserted
Updated
Updated back page information.
Updated
Replaced
Table
Table
Removed
Table
Table
Table
Table 30
Table
Table
Figure
Table
Table
Table
Table
Table
MSRCID4, and MDVAL.
Previous revision’s history listed incorrect cross references. Table 2 is now correctly listed as
Table 27
Table
Table
Table
Table
Table
low state.
Initial Release.
4: Added footnote 2 about junction temperature.
4: Added max. power values for 1000 MHz core frequency.
30: Modified note to t
30: Changed t
30: Added note 3 to t
31: Added note 3 to t
31: Modified values for t
43: Modified note for signal CLK_OUT.
43: PCI1_CLK and PCI2_CLK changed from I/O to I.
52: Added column for Encryption Acceleration.
4: Modified max. power values.
43: Modified notes for signals TSEC1_TXD[3:0], TSEC2_TXD[3:0], TRIG_OUT/READY,
7: Added note 2.
14: Modified min and max values for t
27: Changed LV
4: Modified footnote 4 and changed typical power for the 1000MHz core frequency.
31: Corrected symbols for body rows 9–15, effectively changing them from a high state to a
21: Changed Input Signals: LAD[0:31]/LDP[0:3].
Specifications.”
Figure
and
and Table 31 is now listed as
Section 2.1.2, “Power Sequencing.”
Section 2.1.2, “Power Sequencing.”
Section 17.8, “JTAG Configuration Signals.”
Figure
Table 51. Document Revision History
Table
3, ““Maximum AC Waveforms on PCI interface for 3.3-V Signaling.”
3, “Maximum AC Waveforms on PCI Interface for 3.3-V Signaling.”
31: Modified note 3.
LBKHOZ1
dd
to OV
LBKHOV1
LBKLOV1
LBKSKEW f
and t
LBKHKT
dd
for the supply voltage Ethernet management interface.
LBKHOV2
.
.
Substantive Change(s)
, t
rom 8 to 9
LBKLOV1
Table
values.
DDKHMP
31.
, t
LBKLOV2
, t
LBKLOV3
, t
LBKLOZ1
Document Revision History
Section 10.2, “CPM AC
, and t
LBKLOZ2
.
83