EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 141
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EZ80190AZ050SG
Manufacturer Part Number
EZ80190AZ050SG
Description
IC WEBSERVER 8 BIT 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3866
EZ80190AZ050SG
EZ80190AZ050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80190AZ050SG
Manufacturer:
ZiLOG
Quantity:
135
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PS006614-1208
Table 67. MACC Control Register
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
MACC_IE
6
NOISE
[5:3]
OUT_SHIFT
Value Description
0
1
0
1
000
001
010
011
100
101
110
111
MACC interrupt is disabled.
The MACC interrupt is enabled for the calculation currently being
defined. The MACC generates an interrupt request to the CPU
when it completes this calculation (DONE).
All NOISE bits added to the accumulator using IN_SHIFT are 0.
All NOISE bits added to the accumulator using IN_SHIFT are 1.
No right-shift is performed during READs from the MACC
Accumulator registers by the CPU.
DATA_OUT[40:0] = MACC_ACx[39:0].
Reads from the MACC Accumulator registers by the CPU are
right-shifted by 1 bit with a fill by the sign bit (msb = bit 39).
DATA_OUT[40:0] = {2{MACC_ACx[39]}, MACC_ACx[38:1]}.
Reads from the MACC Accumulator registers by the CPU are
right-shifted by 2 bits with a fill by the sign bit (msb = bit 39).
DATA_OUT[40:0] = {3{MACC_ACx[39]}, MACC_ACx[38:2]}.
Reads from the MACC Accumulator registers by the CPU are
right-shifted by 3 bits with a fill by the sign bit (msb = bit 39).
DATA_OUT[40:0] = {4{MACC_ACx[39]}, MACC_ACx[38:3]}.
Reads from the MACC Accumulator registers by the CPU are
right-shifted by 4 bits with a fill by the sign bit (msb = bit 39).
DATA_OUT[40:0] = {5{MACC_ACx[39]}, MACC_ACx[38:4]}.
Reads from the MACC Accumulator registers by the CPU are
right-shifted by 5 bits with a fill by the sign bit (msb = bit 39).
DATA_OUT[40:0] = {6{MACC_ACx[39]}, MACC_ACx[38:5]}.
Reads from the MACC Accumulator registers by the CPU are
right-shifted by 6 bits with a fill by the sign bit (msb = bit 39).
DATA_OUT[40:0] = {7{MACC_ACx[39]}, MACC_ACx[38:6]}.
Reads from the MACC Accumulator registers by the CPU are
right-shifted by 7 bits with a fill by the sign bit (msb = bit 39).
DATA_OUT[40:0] = {8{MACC_ACx[39]}, MACC_ACx[38:7]}.
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
(MACC_CTL = E7h)
R/W
3
0
R/W
2
0
Product Specification
R/W
1
0
Multiply-Accumulator
R/W
0
0
eZ80190
131
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