EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 34
![IC WEBSERVER 8 BIT 50MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80190AZ050SG
Manufacturer Part Number
EZ80190AZ050SG
Description
IC WEBSERVER 8 BIT 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3866
EZ80190AZ050SG
EZ80190AZ050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80190AZ050SG
Manufacturer:
ZiLOG
Quantity:
135
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Table 2. Register Map (Continued)
PS006614-1208
Address
(hex)
8A
8B
8C
8D
8E
8F
90
91
92
Watchdog Timer
93
94
95
General-Purpose Input/Output Ports
96
97
98
99
9A
9B
9C
Mnemonic
TMR3_DR_L
TMR3_RR_L
TMR3_DR_H
TMR3_RR_H
TMR4_CTL
TMR4_DR_L
TMR4_RR_L
TMR4_DR_H
TMR4_RR_H
TMR5_CTL
TMR5_DR_L
TMR5_RR_L
TMR5_DR_H
TMR5_RR_H
Not Accessible
WDT_CTL
WDT_RR
Not Accessible
PA_DR
PA_DDR
PA_ALT1
PA_ALT2
PB_DR
PB_DDR
PB_ALT1
Name
Timer 3 Data Register—Low Byte
Timer 3 Reload Register—Low Byte
Timer 3 Data Register—High Byte
Timer 3 Reload Register—High Byte
Timer 4 Control Register
Timer 4 Data Register—Low Byte
Timer 4 Reload Register—Low Byte
Timer 4 Data Register—High Byte
Timer 4 Reload Register—High Byte
Timer 5 Control Register
Timer 5 Data Register—Low Byte
Timer 5 Reload Register—Low Byte
Timer 5 Data Register—High Byte
Timer 5 Reload Register—High Byte
Watchdog Timer Control Register
Watchdog Timer Reset Register
Port A Data Register
Port A Data Direction Register
Port A Alternate Register 1
Port A Alternate Register 2
Port B Data Register
Port B Data Direction Register
Port B Alternate Register 1
00/20
Reset
(hex)
XX
XX
XX
FF
FF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Product Specification
1
Access
R/W
R/W
CPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
R
R
R
R
R
R
2
2
Register Map
eZ80190
Page
No.
36
37
36
38
35
36
37
36
38
35
36
37
36
38
41
41
48
48
48
49
48
48
48
24
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