EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 67

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

PS006614-1208
Chip Select x Control Register
Table 20. Chip Select x Control Register
Bit
Position
[7:0]
CS_UBR
Bit
CS 0 Reset
CS 1 Reset
CS 2 Reset
CS 3 Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:5]
CS_WAIT
4
CS_IO
The Chip Select x Control register, listed in
the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip
Select 0 Control register is
registers is
Value Description
00h–
FFh
Value Description
000
001
010
011
100
101
110
111
0
1
00h
.
This bit specifies the upper bound of the Chip Select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining if a Chip Select signal should be generated.
R/W
0 WAIT states are inserted when this Chip Select is active.
1 WAIT state is inserted when this Chip Select is active.
2 WAIT states are inserted when this Chip Select is active.
3 WAIT states are inserted when this Chip Select is active.
4 WAIT states are inserted when this Chip Select is active.
5 WAIT states are inserted when this Chip Select is active.
6 WAIT states are inserted when this Chip Select is active.
7 WAIT states are inserted when this Chip Select is active.
An address match results in a Memory Chip Select.
An address match results in an I/O Chip Select.
7
1
0
0
0
R/W
E8h
6
1
0
0
0
B0h, CS3_CTL = B3h)
, while the reset state for the 3 other Chip Select control
R/W
5
1
0
0
0
(CS0_CTL = AAh, CS1_CTL = ADh, CS2_CTL =
R/W
Table
4
0
0
0
0
20, enables the Chip Selects, specifies
R/W
3
1
0
0
0
R/W
2
0
0
0
0
Chip Selects and Wait States
Product Specification
R/W
1
0
0
0
0
R/W
0
0
0
0
0
eZ80190
57