A80386DX16 Intel, A80386DX16 Datasheet - Page 73

• Manufacturer Part Number: A80386DX16
• Description: IC MPU 32-BIT 5V 16MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX16

• Processor Type: 386DX
• Features: 32-bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 16MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807050

The definition of each bus cycle is given by three
definition signals M IO
same time a valid address is present on the byte
enable signals BE0 – BE3
nals A2–A31 A status signal ADS
when the Intel386 DX issues a new bus cycle defini-
tion and address
Collectively the address bus data bus and all asso-
ciated control signals are referred to simply as ‘‘the
bus’’
When active the bus performs one of the bus cycles
below
1) read from memory space
2) locked read from memory space
3) write to memory space
4) locked write to memory space
5) read from I O space (or coprocessor)
6) write to I O space (or coprocessor)
7) interrupt acknowledge
8) indicate halt or indicate shutdown
Figure 5-8 Fastest Read Cycles with Non-Pipelined Address Timing
W R
and other address sig-
and D C
indicates
Fastest non-pipelined bus cycles consist of T1 and T2
At the
Table 5-2 shows the encoding of the bus cycle defi-
nition signals for each bus cycle See section 5 2 5
Bus Cycle Definition
The data bus has a dynamic sizing feature support-
ing 32- and 16-bit bus size Data bus size is indicated
to the Intel386 DX using its Bus Size 16 (BS16 )
input All bus functions can be performed with either
data bus size
When the Intel386 DX bus is not performing one of
the activities listed above it is either Idle or in the
Hold Acknowledge state which may be detected by
external circuitry The idle state can be identified by
the Intel386 DX giving no further assertions on its
address strobe output (ADS ) since the beginning
of its most recent bus cycle and the most recent
bus cycle has been terminated The hold acknowl-
edge state is identified by the Intel386 DX asserting
its hold acknowledge (HLDA) output
The shortest time unit of bus activity is a bus state A
bus state is one processor clock period (two CLK2
periods) in duration A complete data transfer occurs
during a bus cycle composed of two or more bus
states
Intel386
TM
DX MICROPROCESSOR
231630 –11
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