A80386DX16 Intel, A80386DX16 Datasheet - Page 76

• Manufacturer Part Number: A80386DX16
• Description: IC MPU 32-BIT 5V 16MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX16

• Processor Type: 386DX
• Features: 32-bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 16MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807050

Intel386
5 4 3 Read and Write Cycles
5 4 3 1 INTRODUCTION
Data transfers occur as a result of bus cycles classi-
fied as read or write cycles During read cycles data
is transferred from an external device to the proces-
sor During write cycles data is transferred in the oth-
er direction from the processor to an external de-
vice
Two choices of address timing are dynamically se-
lectable non-pipelined or pipelined After a bus idle
state the processor always uses non-pipelined ad-
dress timing However the NA
put may be asserted to select pipelined address
timing for the next bus cycle When pipelining is se-
lected and the Intel386 DX has a bus request pend-
ing internally the address and definition of the next
cycle is made available even before the current bus
cycle is acknowledged by READY
NA
desired address timing for the next bus cycle
76
Idle states are shown here for diagram variety only Write cycles are not always followed by an idle state An active bus cycle can immediately
follow the write cycle
Figure 5-11 Various Bus Cycles and Idle States with Non-Pipelined Address (zero wait states)
input is sampled each bus cycle to select the
TM
DX MICROPROCESSOR
(Next Address) in-
Generally the
Two choices of physical data bus width are dynami-
cally selectable 32 bits or 16 bits Generally the
BS16
of the bus cycle to confirm the physical data bus size
applicable to the current cycle Negation of BS16
indicates a 32-bit size and assertion indicates a
16-bit bus size
If 16-bit bus size is indicated the Intel386 DX auto-
matically responds as required to complete the
transfer on a 16-bit data bus Depending on the size
and alignment of the operand another 16-bit bus
cycle may be required Table 5-7 provides all details
When necessary the Intel386 DX performs an addi-
tional 16-bit bus cycle using D0 – D15 in place of
D16 – D31
Terminating a read cycle or write cycle like any bus
cycle requires acknowledging the cycle by asserting
the READY
sor inserts wait states into the bus cycle to allow
adjustment for the speed of any external device Ex-
ternal hardware which has decoded the address
and bus cycle type asserts the READY
appropriate time
(Bus Size 16) input is sampled near the end
input Until acknowledged the proces-
231630 –15
input at the