A80386DX16 Intel, A80386DX16 Datasheet - Page 80

• Manufacturer Part Number: A80386DX16
• Description: IC MPU 32-BIT 5V 16MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX16

• Processor Type: 386DX
• Features: 32-bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 16MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807050

Intel386
generated for the two 16-bit bus cycles are closely
related to each other The addresses are the same
except BE0
second cycle This is because data on D0 – D15 was
already transferred during the first 16-bit cycle
Figures 5-14 and 5-15 show cases where assertion
of BS16
plete operand transfer Figure 5-14 illustrates cycles
without wait states Figure 5-15 illustrates cycles
with one wait state In Figure 5-15 cycle 1 the bus
80
Key Dn
dn
e
e
TM
logical data bit n
physical data pin n
requires a second 16-bit cycle for com-
DX MICROPROCESSOR
and BE1
Figure 5-15 Asserting BS16
are always negated for the
(one wait state non-pipelined address)
cycle during which BS16
NA
last T2 state This is to allow the recognition of
BS16
during this state BS16
t17 and t18 BS16
to prevent potential data corruption during split cycle
reads The logic state of BS16
not important The relation of NA
given fully in 5 4 3 4 Pipelined Address but Figure
5-15 illustrates these precautions you need to know
when using BS16
must be negated in the T2 state(s) prior to the
asserted in the final T2 state Also note that
setup and hold timings) in order
with non-pipelined address
must be stable (defined by
is asserted note that
during this time is
and BS16
231630 –19
is