Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 10

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PS010002-0708
BHEN and /BLEN control signals. /MRD is active from the end of T1 until the end of T4
during memory read transactions.
/MSIZE
tion, indicates if it is word size (logic High) or byte size (logic Low). In the latter case, the
addressed memory should be connected to the D15-D8 portion of the data bus, and an
additional memory transaction will automatically be generated to complete a word size
data transfer.
/MWR
addressed memory location should store the data on the data bus, as specified by the /
BHEN and /BLEN control signals. /MWR is active from the end of T2 until the end of T4
during memory write transactions.
/NMI
than the maskable interrupt inputs /INT3-INT0.
/RESET
CLK periods to initialize the Z380 MPU. The effect of /RESET is described in detail in
the Reset section.
/TREFA
goes Low at the end of T2 and returns High at the end of T4 during a memory read, mem-
ory write or refresh transaction. It can be used to control the address multiplexer for a
DRAM interface or as the /RAS signal at higher processor clock rates.
/TREFC
goes Low at the end of T3 and returns High at the end of T4 during a memory read, mem-
ory write or refresh transaction. It can be used as the /CAS signal for DRAM accesses.
/TREFR
goes Low at the end of T1 and returns High at the end of T4 during a memory read, mem-
ory write or refresh transaction. It can be used as the /RAS signal for DRAM accesses.
/UMCS
during a memory read, memory write, or optionally a refresh transaction when accessing
the highest portion of the linear address space within the first 16 Mbytes, but only if this
chip select function is enabled.
V
same voltage externally.
V
to the same voltage externally.
/WAIT
priate, to insert Wait states into the current bus transaction.
The conditioning and characteristics of the Z380 MPU pins under various operation
modes are defined in Table 1.
DD
SS
Ground. These eight pins are the ground references for the device. They must be tied
Power Supply. These eight pins carry power to the device. They must be tied to the
Nonmaskable Interrupt(input, falling edge-triggered). This input has higher priority
Memory Write (output, active Low, tri-state). This signal indicates that the
Wait (input, active Low). This input is sampled by BUSCLK or IOCLK, as appro-
Upper Memory ChipSelect (output, active Low, tri-state). This signal is activated
Memory Size (input, active Low). This input, from the addressed memory loca-
Reset (input, active Low). This input must be active for a minimum of five BUS-
Timing Reference A (output, active Low, tri-state). This timing reference signal
Timing Reference C (output, activeLow, tri-state). This timing reference signal
Timing Reference R (output, active Low, tri-state). This timing reference signal
Z380 Microprocessor
Product Specification
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