Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 101

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BA23-BA14 (Base Address 23-14). In chip select scheme
1, the address signals A23-A16 of a memory transaction
are compared with BA23-BA16 for a match, for those bits
programmed for address matching in the Mid-range
Memory Chip Select Register 1. The contents of this
register have no effects in chip select scheme 2. Note that
in order for one of /MCS3-/MCS0 to go active in a memory
transaction in chip select scheme 1, the ENM1 bit in the
Memory Selects Master Enable Register (described later)
has to be at logic 1, all the address signals A31-A24 at logic
0s, and for those bits programmed for address matching,
A23-A14 matching BA23-BA14. For the intended usage to
maintain the mid-range memory area as a single block,
MA23-MA14 (in that order) should be programmed for
address matching with contiguous 1s followed by contigu-
ous 0s. Note also that /MCS3-/MCS0 can be individually
enabled to go active during refresh transactions, indepen-
dent of the value programmed into the Memory Selects
Master Enable Register.
Lower Memory Wait Register
T1W2-T1W0 (T1 Waits). This binary field defines up to
seven T1 wait states to be inserted in transactions access-
ing the lower memory area.
T2W1-T2W0 (T2 Wait States). This binary field defines up
to three T2 wait states to be inserted in transactions
accessing the lower memory area.
T3W2-T3W0 (T3 Waits). This binary field defines up to
seven T3 wait states to be inserted in transactions access-
ing the lower memory area.
Figure 39. Mid-range Memory Chip Select Register 3
7
MMCSR3: 00000007H
R/W
BA23
0
BA22 BA21 BA20 BA19 BA18 BA17 BA16
0
0
0
0
0
0
0
0
<- Reset Value
Upper Memory Wait Register
T1W2-T1W0 (T1 Waits). This binary field defines up to
seven T1 wait states to be inserted in transactions access-
ing the upper memory area.
T2W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in transactions access-
ing the upper memory area.
T3W2-T3W0 (T3 Waits). This binary field defines up to
seven T3 wait states to be inserted in transactions access-
ing the upper memory area.
7
7
LMWR: 00000008H
R/W
UMWR: 00000009H
R/W
T1W2
T1W2
1
1
Figure 40. Lower Memory Waits Register
T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
Figure 41. Upper Memory Waits Register
1
1
1
1
1
1
1
1
1
1
1
1
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1
1
0
0
<- Reset Value
<- Reset Value
T3 Waits
T3 Waits
T2 Waits
T2 Waits
T1 Waits
T1 Waits