MC68EC000EI16 Freescale Semiconductor, MC68EC000EI16 Datasheet - Page 196

• Manufacturer Part Number: MC68EC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Integer Instructions
DIVS, DIVSL
Operation:
Assembler
Syntax:
Attributes:
Description: Divides the signed destination operand by the signed source operand and
Condition Codes:
4-92
stores the signed result in the destination. The instruction uses one of four forms. The
word form of the instruction divides a long word by a word. The result is a quotient in
the lower word (least significant 16 bits) and a remainder in the upper word (most
significant 16 bits). The sign of the remainder is the same as the sign of the dividend.
The first long form divides a long word by a long word. The result is a long quotient; the
remainder is discarded.
The second long form divides a quad word (in any two data registers) by a long word.
The result is a long-word quotient and a long-word remainder.
The third long form divides a long word by a long word. The result is a long-word quo-
tient and a long-word remainder.
Two special conditions may arise during the operation:
X—Not affected.
N — Set if the quotient is negative; cleared otherwise; undefined if overflow or divide
Z — Set if the quotient is zero; cleared otherwise; undefined if overflow or divide by
V — Set if division overflow occurs; undefined if divide by zero occurs; cleared oth-
C — Always cleared.
1. Division by zero causes a trap.
2. Overflow may be detected and set before the instruction completes. If the in-
—
X
struction detects an overflow, it sets the overflow condition code, and the oper-
ands are unaffected.
by zero occurs.
zero occurs.
erwise.
N
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Destination
DIVS.W < ea > ,Dn32/16
*DIVS.L < ea > ,Dq
*DIVS.L < ea > ,Dr:Dq
*DIVSL.L < ea > ,Dr:Dq
Size = (Word, Long)
*Applies to MC68020, MC68030, MC68040, CPU32 only
Z
V
C
0
Source
Signed Divide
(M68000 Family)
Destination
32/32
64/32
32/32
16r – 16q
32q
32r – 32q
32r – 32q
DIVS, DIVSL
MOTOROLA