MC68EC000EI16 Freescale Semiconductor, MC68EC000EI16 Datasheet - Page 23

• Manufacturer Part Number: MC68EC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Introduction
1.3.6 Transparent Translation/access Control Registers
Transparent translation is actually a misnomer since the whole address space transparently
translates in an embedded control environment with no on-chip MMU present as well as in
processors that have built-in MMUs. For processors that have built-in MMUs, such as the
MC68030, MC68040, and MC68LC040, the transparent translation (TT) registers define
blocks of logical addresses that are transparently translated to corresponding physical
addresses. These registers are independent of the on-chip MMU. For embedded
controllers, such as the MC68EC030 and MC68EC040, the access control registers (AC)
are similar in function to the TT registers but just named differently. The AC registers, main
function are to define blocks of address space that control address space properties such
as cachability. The following paragraphs describe these registers.
1.3.6.1 TRANSPARENT TRANSLATION/ACCESS CONTROL REGISTER FIELDS FOR
THE M68030. Figure 1-9 illustrates the MC68030 transparent translation/MC68EC030
access control register format.
1-12
Address Base
Address Mask
Figure 1-9. MC68030 Transparent Translation/MC68EC030 Access Control Register
31
15
E
This 8-bit field is compared with address bits A31 – A24. Addresses that match in this
This 8-bit field contains a mask for the address base field. Setting a bit in this field causes
comparison (and are otherwise eligible) are transparently translated/access controlled.
the corresponding bit of the address base field to be ignored. Blocks of memory larger
than 16 Mbytes can be transparently translated/accessed controlled by setting some log-
ical address mask bits to ones. The low-order bits of this field normally are set to define
contiguous blocks larger than 16 Mbytes, although this is not required.
14
0
13
For the paged MMU related supervisor registers, please refer to
the appropriate user’s manual for specific programming detail.
0
ADDRESS BASE
12
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
11
0
10
CI
R/W
9
RWM
Format
24
8
NOTE
23
0
7
6
FC BASE
ADDRESS MASK
4
0
3
2
FC MASK
MOTOROLA
16
0