MC68EC000EI16 Freescale Semiconductor, MC68EC000EI16 Datasheet - Page 519

• Manufacturer Part Number: MC68EC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PTEST
MOTOROLA
The MMU status register contains the results of the search. The values in the fields of
the MMU status register for an address translation cache search are given in the fol-
lowing table:
Bus Error (B)
Limit (L)
Supervis or
Violatio n (S)
Write
Protecte d (W)
Invalid (I)
Modified (M)
Transparent (T)
Number of
Levels (N)
MMUSR Bit
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
This bit is set if the bus error bit is set in the
ATC entry for the specified logical address.
This bit is cleared.
This bit is cleared.
The bit is set if the WP-bit of the ATC entry
is set. It is undefined if the I-bit is set.
This bit indicates an invalid translation. The
I- bit is set if the translation for the specified
logical address is not resident in the ATC
or if the B-bit of the corresponding ATC en-
try is set.
This bit is set if the ATC entry correspond-
ing to the specified address has the modi-
fied bit set. It is undefined if the I-bit is set.
This bit is set if a match occurred in either
(or both) of the transparent translation reg-
isters (TT0 or TT1).
This 3-bit field is set to zero.
PTEST, Level 0
Test a Logical Address
(MC68030 only)
This bit is set if a bus error is encountered
during the table search for the PTEST in-
struction.
This bit is set if an index exceeds a limit
during the table search.
This bit is set if the S-bit of a long (S) format
table descriptor or long format page de-
scriptor encountered during the search is
set and if the FC2-bit of the function code
specified by the PTEST instruction is not
equal to one. The S-bit is undefined if the I-
bit is set.
This bit is set if a descriptor or page de-
scriptor is encountered with the WP-bit set
during the table search. The W-bit is unde-
fined if the I-bit is set.
This bit indicates an invalid translation. The
I-bit is set if the DT field of a table or a page
descriptor encountered during the search
is set to invalid or if either the B or L bits of
the MMUSR are set during the table
search.
This bit is set if the page descriptor for the
specified address has the modified bit set.
It is undefined if I-bit is set.
This bit is set to zero.
This 3-bit field contains the actual number
of tables accessed during the search.
Supervisor (Privileged) Instructions
PTEST, Levels 1–7
PTEST
6-65