MPC8347CVRAGDB Freescale Semiconductor, MPC8347CVRAGDB Datasheet - Page 78

IC MPU POWERQUICC II 620-PBGA

MPC8347CVRAGDB

Manufacturer Part Number
MPC8347CVRAGDB
Description
IC MPU POWERQUICC II 620-PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheets

Specifications of MPC8347CVRAGDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
400MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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3
4
Clocking
19.1
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk).
78
The DDR data rate is 2× the DDR memory bus frequency.
The local bus frequency is ½, ¼, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBIUCM]).
System PLL Configuration
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Section 19, “Clocking,”
Table 60. System PLL Multiplication Factors
RCWL[SPMF]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
the LBIUCM, DDRCM, and SPMF parameters in the reset
System PLL Multiplication Factor
Reserved
× 16
× 10
× 11
× 12
× 13
× 14
× 15
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
Table 60
shows the multiplication factor
Freescale Semiconductor
Table 61

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