MPC8343CVRAGDB Freescale Semiconductor, MPC8343CVRAGDB Datasheet

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... To locate published errata or updates for this document, refer to the MPC8343EA product summary page on our website, as listed on the back cover of this document, or contact your local Freescale sales office. © 2006–2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8343EAEC Rev. 10, 10/2010 Contents 1 ...

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... MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev NOTE e300 Core 2 C Interrupt 32KB 32KB Controller D-Cache I-Cache 10/100/1000 10/100/1000 Ethernet Ethernet Figure 1. MPC8343EA Block Diagram for Figure 1 shows the major functional DDR SDRAM Local Bus Controller SEQ PCI DMA Freescale Semiconductor ...

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... Memory prefetching of PCI read accesses and support for delayed read transactions — Posting of processor-to-PCI and PCI-to-memory writes — On-chip arbitration supporting five masters on PCI — Accesses to all PCI address spaces — Parity supported — Selectable hardware-enforced coherency MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Overview 3 ...

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... USB on-the-go mode with both device and host functionality — Complies with USB specification Rev. 2.0 — Can operate as a stand-alone USB device – One upstream facing port – Six programmable USB endpoints MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Concurrent execution across multiple channels with programmable bandwidth control — Handshaking (external control) signals for all channels: DMA_DREQ[0:3], DMA_DACK[0:3], DMA_DDONE[0:3] — All channels accessible to local core and remote PCI masters MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 2 C interfaces 2 C-1 EPROM by boot sequencer embedded ...

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... JTAG I/O voltage MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Table 1. Absolute Maximum Ratings Symbol Max Value Unit Notes –0.3 to 1.32 V — –0.3 to 1.32 V — –0.3 to 2.75 V — –0.3 to 1.98 –0.3 to 3.63 V — –0.3 to 3.63 V — Freescale Semiconductor ...

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... Table 2. Recommended Operating Conditions Parameter Core supply voltage PLL supply voltage DDR and DDR2 DRAM I/O voltage Three-speed Ethernet I/O supply voltage Three-speed Ethernet I/O supply voltage MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Symbol and JTAG signals ...

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... Figure 2. Overshoot/Undershoot Voltage for GV MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Symbol OV DD must track each other and must vary in the same direction—either in the positive GND Not to Exceed 10 interface Recommended Unit Value 3.3 V ± 330 /OV / Freescale Semiconductor Notes — ...

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... To minimize the time that I/O pins are actively driven recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up. MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 11 ns (Min) +7 ...

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... Dhrystone benchmark J target, and I 105°C, and Unit Comments (2.5 V) — — W — — W — — W — — W — — W — — W — — W — — W — — W Freescale Semiconductor Unit — — — — — — — — — ...

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... The primary clock source for the MPC8343EA can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. (CLKIN/PCI_CLK) AC timing specifications for the device. Parameter/Condition CLKIN/PCI_CLK frequency CLKIN/PCI_CLK cycle time CLKIN/PCI_CLK rise and fall time MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor DDR2 DDR1 ...

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... G125H G125 45 47 — — — — ±150 ps Typical Max Unit 125 — MHz 8 — ns — ns 0.75 1.0 — — ±150 ps = 2.5 V and from 0.6 and 2.7 V for DD for the duty cycle for 10Base-T and 100Base-T Freescale Semiconductor Notes — — ...

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... PCI agent mode Input hold time for POR configuration signals with respect to negation of HRESET Time for the MPC8343EA to turn off POR configuration signals with respect to the assertion of HRESET MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Symbol Condition Min V — ...

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... Section 19, “Clocking.” (typ) = 2.5 V and DDR2 SDRAM NOTE Section 22.1, “Part Numbers Fully Addressed by This . Symbol Min GV 1.71 DD Min Max Unit Notes 1 — PCI_SYNC_IN Max Unit Notes μs 100 — 122,880 csb_clk cycles 1, 2 (typ (typ Max Unit Notes 1. Freescale Semiconductor ...

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... I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (V = 1.95 V) OUT MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 0.49 × REF V MV – 0.04 TT REF ...

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... DD Symbol Min V — 0.25 IH REF (typ — (typ Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT REF Min Max Unit μA — 500 (typ Max Unit MV – 0.25 V REF — V Freescale Semiconductor — Notes 1 1 Note 1 Notes — — ...

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... DISKEW value CISKEW 3. This specification applies only to the DDR interface. Figure 4 illustrates the DDR input timing diagram showing the t MCK[n] MCK[n] MDQS[n] MDQ[x] MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor of 2.5 ± 5%. DD Symbol Min V — 0.31 IH REF of (1.8 or 2.5 V) ± ...

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... DDKHDS, t DDKLDS 700 775 1100 1200 t DDKHDX, t DDKLDX 700 900 1100 1200 Max Unit Notes — — — — — — — — — — — — — — — — 0 — — — — — — — — Freescale Semiconductor ...

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... All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t symbol conventions described in note 1. Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t MCK[n] MCK[n] MDQS MDQS MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor of (1.8 or 2.5 V) ± 5 Symbol –0.5 × DDKHMP t ...

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... MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev MCK t ,t DDKHAS DDKHCS t ,t DDKHAX DDKHCX NOOP t DDKHMP t DDKHMH t DDKHDS t DDKLDS DDKHDX = 50 Ω Ω Figure 7. DDR AC Test Load Symbol DDKHME t DDKLDX Min Max 0.3 DD –0.3 0.8 — ±5 Freescale Semiconductor Unit V V μA ...

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... Hewlett-Packard Reduced Pin-Count Interface for Gigabit Ethernet Physical Layer Device Specification, Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.” MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Symbol V V Table 22. DUART AC Timing Specifications ...

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... LV + 0.3 DD — –0.3 0.90 — 40 –600 — and Table 2. supply. Min Max 2.37 2.63 = Min 2. 0 Min GND – 0.3 0.40 = Min 1 0 Min –0.3 0.70 — 10 –15 — and Table 2. Freescale Semiconductor Unit μA μA Unit μA μA ...

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... MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 8 shows the MII transmit AC timing diagram. TX_CLK TXD[3:0] TX_EN TX_ER MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor /OV of 3.3 V ± 10 Symbol t MTX ...

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... Figure 10. MII Receive AC Timing Diagram Min Typ Max — 400 — — 40 — 35 — 65 10.0 — — 10.0 — — 1.0 — 4.0 1.0 — 4.0 symbolizes MII receive timing MRDVKH clock reference (K) going to MRX Ω MRXR t MRDXKH Freescale Semiconductor Unit for inputs MRX ...

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... Duty cycle reference This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention. MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Specifications of 2.5 V ± 5 Symbol ...

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... RXDV RXERR Section 8.1, “Three-Speed Ethernet Controller Characteristics.” Table 28 and Symbol Conditions LV — –1 Min 1 Min — Min — Min RGT t SKRGT t SKRGT Table 29. Min Max 2.37 2.63 2. 0.3 DD GND – 0.3 0.40 1.7 — –0.3 0.70 Freescale Semiconductor Unit ...

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... At recommended operating conditions with LV Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Symbol Conditions ...

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... V ± 10% or 2.5 V ± 5 Symbol Min t — MDHF (first two letters of functional block)(signal)(state)(reference)(state) for outputs. For example MDC t t MDCF MDCH t MDDVKH t MDDXKH t MDKHDX Typ Max Unit — for inputs symbolizes management data MDKHDX t MDCR Freescale Semiconductor Notes — ...

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... For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Table 31. USB DC Electrical Characteristics Symbol ...

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... Low-level output voltage MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Ω Ω Figure 13. USB AC Test Load t USIVKH t t USKHOV USKHOX Figure 14. USB Signals Symbol USIXKH Min Max Unit 0 –0.3 0.8 V μA — ±5 OV – 0.2 — — 0.2 V Freescale Semiconductor ...

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... For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 1 Symbol t LBK ...

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... LCLK0 to 0.4 × Ω Figure 15. Local Bus C Test Load 9 Min Max Unit 15 — — ns 1.0 — ns 1.5 — — ns 2.5 — ns — — symbolizes local bus timing (LB) LBIXKH1 of the signal in question for 3 Ω L Freescale Semiconductor Notes for inputs ...

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... Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output Signals: LAD[0:31]/LDP[0:3] LALE Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor t LBIVKH t LBKHOV t LBKHOZ t t LBKHOV LBKHOX ...

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... LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 t LBKHOZ t LBKLOV t LBIVKH t LBKHOZ t LBKLOV t LBIXKH2 t LBIXKH1 t LBIXKH t LBIXKH t LBIVKH Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor t LBKHOZ t LBKLOV t LBIVKH t t ...

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... Input current Output high voltage MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 Symbol Condition V — — — –8 LBIXKH2 t LBIXKH1 Min Max Unit OV – –0.3 0.8 V μA — ±5 2.4 — V Freescale Semiconductor ...

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... JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data Output hold times: Boundary-scan data MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Symbol Condition 8 3.2 mA ...

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... JTG VM = Midpoint Voltage ( TRST VM = Midpoint Voltage (OV DD /2) Figure 24. TRST Timing Diagram 1 (continued) Min Max Unit the midpoint of the signal in question. TCLK Figure symbolizes JTAG device timing JTDVKH clock reference (K) going JTG Ω JTGR t JTGF VM Freescale Semiconductor Notes 5, 6 13). for inputs ...

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... JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 26. Test Access Port Timing Diagram MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 25. Boundary-Scan Timing Diagram VM ...

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... V DD 0.2 × 250 μA –10 10 — Min Max f 0 400 I2C t 1.3 — I2CL t 0.6 — I2CH t 0.6 — I2SVKH t 0.6 — I2SXKL t 100 — I2DVKH t — — I2DXKL 0.9 Freescale Semiconductor Notes Unit kHz μs μs μs μs ns μs ...

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... I2CL SCL t I2SXKL S MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Electrical Specifications (continued) 5 (first two letters of functional block)(signal)(state)(reference)(state) for outputs. For example timing (I2) for the time that the data with respect to the start condition (S) clock reference (K) going to the low (L) state or hold time ...

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... Table IN Table 41 provides the PCI AC timing specifications at 66 MHz. 2 Symbol t PCKHOV t PCKHOX t PCKHOZ t PCIVKH Min Max 0.3 DD –0.3 0.8 — ± – 0.2 — DD — 0 Min Max Unit — 6 — ns — 3.0 — ns Freescale Semiconductor Unit V V μ Notes ...

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... For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. Figure 29 provides the AC test load for PCI. Output MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 2 Symbol Min t 0 PCIXKH (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... PCIVKH Figure 30. PCI Input AC Timing Diagram t PCKHOV Figure 31. PCI Output AC Timing Diagram Symbol Condition V — — — – PCIXKH t PCKHOX t PCKHOZ Min Max Unit 2 0.3 DD –0.3 0.8 — ±5 2.4 — — 0.5 — 0.4 Freescale Semiconductor V V μ ...

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... Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external synchronous logic. GPIO inputs must be valid for at least t MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 1 Symbol t TIWID ns to ensure proper operation ...

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... PICWID Table 49. SPI DC Electrical Characteristics Symbol Condition V — — Min Max Unit 2 0 –0.3 0.8 V μA — ±5 — 0.5 V — 0 Symbol Min t 20 PICWID Min Max 2 0.3 DD –0.3 0.8 Freescale Semiconductor Notes — — — Unit ns Unit V V ...

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... SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). Figure 32 provides the AC test load for the SPI. Output MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Symbol Condition I — IN ...

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... Package outline Interconnects Pitch Module height (maximum) MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Table 50. Note that although the specifications t NEIXKH t NEKHOX t NIIXKH t NIIVKH t NIKHOX Section 18.1, “Package Parameters for the MPC8343EA PBGA,” × 620 1.00 mm 2.46 mm Freescale Semiconductor ...

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... Module height (typical) Module height (minimum) Solder balls Ball diameter (typical) MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 2. Sn/36 Pb/2 Ag (ZQ package) 96.5 Sn/3.5Ag (VR package) 0.60 mm Package and Pin Listings 49 ...

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... Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 35. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8343EA PBGA MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... PCI1_GNT0 PCI1_GNT1/CPCI1_HS_LED PCI1_GNT2/CPCI1_HS_ENUM PCI1_GNT[3:4] M66EN MDQ[0:31] MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Package Pin Number PCI D20 B21 E19, D17, A16, A18, B17, B16, D16, B18, E17, E16, A15, C16, D15, D14, C14, A12, D12, B11, C11, E12, A10, ...

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... I/O GV — DD I/O GV — DD I/O GV — — — DD I/O GV — DD I/O GV — — — — — — — — — — — DD I/O — 9 I/O — 9 I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — — — DD Freescale Semiconductor ...

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... GPIO1[5]/DMA_DDONE1/ GTM1_TOUT2/GTM2_TOUT1 GPIO1[6]/DMA_DREQ2/GTM1_TIN3/ GTM2_TIN4 GPIO1[7]/DMA_DACK2/GTM1_TGATE3/ GTM2_TGATE4 GPIO1[8]/DMA_DDONE2/ GTM1_TOUT3 GPIO1[9]/DMA_DREQ3/GTM1_TIN4/ GTM2_TIN3 GPIO1[10]/DMA_DACK3/ GTM1_TGATE4/GTM2_TGATE3 GPIO1[11]/DMA_DDONE3/ GTM1_TOUT4/GTM2_TOUT3 MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Package Pin Number D4, A3 General Purpose I/O Timers D27 ...

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... I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — DD I/O OV — — — — — — I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — DD1 I DD1 I LV — DD1 I/O OV — DD I/O LV — DD1 DD1 I LV — DD1 Freescale Semiconductor ...

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... UART_SIN[1:2]/MSRCID[2:3]/ LSRCID[2:3] UART_CTS[1]/MSRCID4/LSRCID4 UART_CTS[2]/MDVAL/LDVAL UART_RTS[1:2] IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Package Pin Number U24 L28 W26, W24, Y28, Y27 N25 V28, V27, V26, W28 W27 N24 P28 AC28 ...

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... H28 M24 J27 K26 Test F28 T3 PMC K27 System Control K28 M25 L27 Thermal Management B15 Power Pin Type Notes Supply I/O OV — DD I/O OV — DD I/O OV — — — — — — — — — — — — 8 Freescale Semiconductor ...

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... DD1 LV DD2 V DD MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Package Pin Number Power and Ground Signals C15 U1 AF9 U2 A2, B1, B2, D10, D18, E6, E14, E22, F9, F12, F15, F18, F21, F24, G5, H6, J23, L4, L6, L12, L13, L14, L15, L16, L17, ...

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... AE23, AF1, AF5, AF6, AF8, AF24, AG1, AG3, AG4, AG7, AG8, AG9, AG10, AH2, AH3, AH5, AH8, AH9, V5, V2 DD1 Power Pin Type Notes Supply PCI, 10/100 OV — DD Ethernet, and other standard (3 DDR — reference voltage I DDR — reference voltage — — — Freescale Semiconductor ...

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... PCI agent devices in the system, to allow the MPC8343EA to function. When the device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal should be tied to GND. MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor e300 Core core_clk Core PLL ...

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... Table 52. Configurable Clock Units Default Frequency csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk Off, csb_clk Section 22.1, “Part Numbers Fully Addressed by This Options Freescale Semiconductor ...

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... RCWL[LBIUCM]). 19.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. encodings for the system PLL. MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Table 53. Operating Frequencies for PBGA 266 MHz 200–266 2 3 Table 54. System PLL Multiplication Factors ...

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... Input Clock Frequency (MHz) 16.67 25 33.33 csb_clk Frequency (MHz) 100 100 133 125 166 150 200 175 233 200 266 225 300 250 333 275 300 325 233 250 266 Freescale Semiconductor Table 55 2 66.67 133 200 266 333 ...

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... Low 1011 Low 1100 Low 1101 Low 1110 Low 1111 Low 0000 High 0010 MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Input Clock Frequency (MHz) csb_clk : 16.67 2 Input Clock Ratio csb_clk Frequency (MHz Input Clock Frequency (MHz) csb_clk : 16 ...

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... Input Clock Frequency (MHz) 25 33.33 csb_clk Frequency (MHz) 100 150 200 133 200 266 166 250 333 200 300 233 266 VCO Divider PLL bypassed (PLL off, csb_clk clocks core directly Freescale Semiconductor 2 66.67 1 ...

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... MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor core_clk : csb_clk Ratio 6 0 2:1 0 2:1 0 2:1 0 2:1 1 2.5:1 1 2.5:1 1 2.5:1 1 2.5:1 0 3:1 0 3:1 ...

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... Freescale Semiconductor ...

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... ambient temperature for the package (° junction-to-ambient thermal resistance (°C/W) θ power dissipation in the package (W) D MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor × where I/O I/O , can be obtained from the equation: J × θ ...

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... The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev – × θ Ψ determine the junction temperature and a measure of the JT Ψ × are possible. A Freescale Semiconductor ...

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... AAVID 31 × 35 × pin fin Wakefield, 53 × 53 × pin fin Wakefield, 53 × 53 × pin fin Wakefield, 53 × 53 × pin fin MEI, 75 × 85 × adjacent board, extrusion MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor + R θ θ For instance, the user can change the size of the heat θ ...

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... P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev × PBGA Air Flow Thermal Resistance 1 m/s 7.7 2 m/s 6.6 1 m/s 6.9 603-224-9988 408-567-8082 818-842-7277 408-436-8770 800-522-2800 603-635-5102 Freescale Semiconductor ...

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... From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance where junction temperature (° case temperature of the package (°C) C MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor × θ 781-935-4850 800-248-2481 888-642-7674 800-347-4572 Thermal 71 ...

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... V Figure 37, one to each of the four AV 10 Ω 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND Figure 37. PLL Power Supply Filter Circuit respectively). The through a DD pins (or L2AV ) DD DD Freescale Semiconductor DD DD ...

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... GND. Then the value of each resistor is varied until the pad voltage is OV output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and R MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor required. Unused active high inputs should be ...

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... PCI Output Clocks (Not Including PCI (Including Output Clocks) PCI_SYNC_OUT) 25 Target 42 Target 25 Target 42 Target NA Table 105°C. j and R are designed to be close to each SW2 SW1 . The measured voltage is term × (V ÷ source term 1 DDR DRAM Symbol 20 Target Target DIFF Freescale Semiconductor – 1 Unit ...

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... Each part number also contains a revision code that refers to the die mask revision number. For available frequency configuration MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor NOTE Ordering Information ...

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... YWWLAZ PBGA Notes : ATWLYYWW is the traceability code. CCCCC is the country code. MMMMM is the mask number. YWWLAZ is the assembly traceability code Processor Platform Revision 3 Frequency Frequency Level e300 core D = 266 B = 3.1 speed AD = 266 AG = 400 SVR (Rev. 3.0) 8056_0030 8057_0030 Freescale Semiconductor ...

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... Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified T from 900 ps to 775 ps. MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Table 64. Document Revision History Substantive Change(s) 51, added overbar to LCS[4] and LCS[5] signals. In Requirements, updated the list of open drain type pins. ...

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... Substantive Change(s) + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0. 0.3; changed low-level input voltage values to min = (–0.3) and max = 0. 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8. DD and VIL in Table 40Table 44,“PCI DC Electrical IH Freescale Semiconductor ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...