IS80C286-20 Intersil, IS80C286-20 Datasheet - Page 10

• Manufacturer Part Number: IS80C286-20
• Description: IC CPU 16BIT 5V 20MHZ 68-PLCC
• Manufacturer: Intersil

Specifications of IS80C286-20

• Processor Type: 80C286 16-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

LOGICALS
SHIFTS
ROTATES
CONDITIONAL TRANSFERS
TABLE 2D. SHIFT/ROTATE LOGICAL INSTRUCTIONS
SHL/SAL
BOUND
ENTER
LEAVE
TEST
NOT
AND
XOR
SHR
ROR
RCR
SAR
ROL
RCL
OR
JNP/JPO
JA/JNBE
JAE/JNB
JB/JNAE
JBE/JNA
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JNE/JNZ
JP/JPE
TABLE 2E. HIGH LEVEL INSTRUCTIONS
JE/JZ
JNO
JNC
JNS
JO
JC
JS
“Not” byte or word
“And” byte or word
“Inclusive or” byte or word
“Exclusive or” byte or word
“Test” byte or word
Shift logical/arithmetic left byte or word
Shift logical right byte or word
Shift arithmetic right byte or word
Rotate left byte or word
Rotate right byte or word
Rotate through carry left byte or word
Rotate through carry right byte or word
Format stack for procedure entry
Restore stack for procedure exit
Detects values outside prescribed range
Jump if above/not below nor equal
Jump if above or equal/not below
Jump if below/not above nor equal
Jump if below or equal/not above
Jump if carry
Jump if equal/zero
Jump if greater/not less nor equal
Jump if greater or equal/not less
Jump if less/not greater nor equal
Jump if less or equal/not greater
Jump if not carry
Jump if not equal/not zero
Jump if not overflow
Jump if not parity/parity odd
Jump if not sign
Jump if overflow
Jump if parity/parity even
Jump if sign
TABLE 2G. PROGRAM TRANSFER INSTRUCTIONS
80C286
10
FLAG OPERATIONS
EXTERNAL SYNCHRONIZATION
NO OPERATION
EXECUTION ENVIRONMENT CONTROL
TABLE 2F. PROCESSOR CONTROL INSTRUCTIONS
SMSW
LMSW
LOCK
WAIT
CMC
NOP
STC
CLC
STD
CLD
ESC
HLT
UNCONDITIONAL TRANSFERS
ITERATION CONTROLS
INTERRUPTS
STl
CLl
LOOPNE/LOOPNZ
LOOPE/LOOPZ
LOOP
CALL
JCXZ
INTO
lRET
RET
JMP
INT
Set carry flag
Clear carry flag
Complement carry flag
Set direction flag
Clear direction flag
Set interrupt enable flag
Clear interrupt enable flag
Halt until interrupt or reset
Wait for TEST pin active
Escape to extension processor
Lock bus during next instruction
No operation
Load machine status word
Store machine status word
Call procedure
Return from procedure
Jump
Loop
Loop if equal/zero
Loop if not equal/not zero
Jump if register CX = 0
Interrupt
Interrupt if overflow
Interrupt return