IS80C286-20 Intersil, IS80C286-20 Datasheet - Page 24

• Manufacturer Part Number: IS80C286-20
• Description: IC CPU 16BIT 5V 20MHZ 68-PLCC
• Manufacturer: Intersil

Specifications of IS80C286-20

• Processor Type: 80C286 16-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

NOTES:
NOTE: Carry out in offset calculations is ignored.
The lRET and POPF instructions do not perform some of
their defined functions if CPL is not of sufficient privilege
(numerically small enough). Precisely these are:
• The IF bit is not changed if CPL is greater than IOPL.
• The lOPL field of the flag word is not changed if CPL is
No exceptions or other indication are given when these con-
ditions occur.
Exceptions
The 80C286 detects several types of exceptions and inter-
rupts in protected mode (see Table 17). Most are restartable
after the exceptional condition is removed. Interrupt handlers
for most exceptions can read an error code, pushed on the
stack after the return address, that identifies the selector
involved (0 if none). The return address normally points to
the failing instruction including all leading prefixes. For a pro-
cessor extension segment overrun exception, the return
6. When a PUSHA or POPA instruction attempts to wrap around the stack segment, the machine state after the exception will not be restartable
7. These exceptions indicate a violation to privilege rules or usage rules has occurred. Restart is generally not attempted under those conditions.
Write into code segment
Read from execute-only code segment
Write to read-only data segment
Segment limit exceeded (See Note)
CPL ≠ 0 when executing the following instructions:
CPT > IOPL when executing the following
instructions:
INTERRUPT
greater than 0.
VECTOR
LIDT, LLDT, LGDT, LTR, LMSW, CTS, HLT
INS, IN, OUTS, OUT, STI, CLI, LOCK
because stack segment wrap around is not permitted. This condition is identified by the value of the saved SP being either 0000(H), 0001(H),
FFFE(H), or FFFF(H).
10
11
12
13
8
9
TABLE 16. PRIVILEGED INSTRUCTION CHECKS
TABLE 15. OPERAND REFERENCE CHECKS
ERROR DESCRIPTION
ERROR DESCRIPTION
Double exception detected
Processor extension segment overrun
Invalid task state segment
Segment not present
Stack segment overrun or stack segment not present
General protection
FUNCTION
TABLE 17. PROTECTED MODE EXCEPTIONS
EXCEPTION
EXCEPTION
NUMBER
NUMBER
12 or 13
13
13
13
13
13
80C286
24
address will not point at the ESC instruction that caused the
exception; however, the processor extension registers may
contain the address of the failing instruction.
These exceptions indicate a violation to privilege rules or
usage rules has occurred. Restart is generally not attempted
under those conditions.
All these checks are performed for all instructions and can
be split into three categories: segment load checks (Table
14), operand reference checks (Table 15), and privileged
instruction checks (Table 16). Any violation of the rules
shown will result in an exception. A not-present exception
causes exception 11 or 12 and is restartable.
SPECIAL OPERATIONS
Task Switch Operation
The 80C286 provides a built-in task switch operation which
saves the entire 80C286 execution state (registers, address
space, and a link to the previous task), loads a new execution
state, and commences execution in the new task. Like gates,
the task switch operation is invoked by executing an inter-seg-
ment JMP or CALL instruction which refers to a Task State
Segment (TSS) or task gate descriptor in the GDT or LDT. An
INT instruction, exception, or external interrupt may also
invoke the task switch operation by selecting a task gate
descriptor in the associated IDT descriptor entry.
The TSS descriptor points at a segment (see Figure 18) con-
taining the entire 80C286 execution state while a task gate
descriptor contains a TSS selector. The limit field of the
descriptor must be greater than 002B(H).
Each task must have a TSS associated with it. The current
TSS is identified by a special register in the 80C286 called
the Task Register (TR). This register contains a selector
referring to the task state segment descriptor that defines
the current TSS. A hidden base and limit register associated
with TR are loaded whenever TR is loaded with a new selec-
tor. The IRET instruction is used to return control to the task
that called the current task or was interrupted. Bit 14 in the
flag register is called the Nested Task (NT) bit. It controls the
RETURN ADDRESS
INSTRUCTION?
AT FALLING
Yes
Yes
Yes
Yes
Yes
No
RESTARTABLE?
Yes (Note 6)
No (Note 7)
No (Note 7)
No (Note 7)
ALWAYS
Yes
Yes
ERROR CODE
ON STACK?
Yes
Yes
Yes
Yes
Yes
No