MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 147

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

B
6 . 1 . 3
6.1.3.1 SINGLE ENTRY MODE.
6.1.2.2
6-10
f i l l e d . Refer to SECTION 7 BUS OPERATION for detailed information about
the bus cycles required for both modes.
the case of a cache miss on the write, the allocation of a new cache entry
for the data being written is controlled by the WA bit. Table search accesses,
The bus controller can load either cache in either of two ways:
of a cache line. In the burst fill mode, an entire line (four long words) can be
external hardware, the bus controller transfers a single long word for the
corresponding cache entry. An entire long word is required. If the port size
When a device cannot supply its entire port width of data, regardless of the
for 8-bit transfers. The MC68030 assumes that a 32-bit termination signal for
the bus cycle indicates availability of 32 valid data bits, even if only 16 or 8
cycle is always forced to miss in the data cache. However, if the system
allows internal caching of read-modify-write cycle operands (CLOUT and CIIN
both negated), the processor either uses the data read from memory to
update a matching entry in the data cache or creates a new entry with the
read data in the case of no matching entry. The write portion of a read-
modify-write operation also updates a matching entry in the data cache. In
however, are completely ignored by the data cache; it is never updated for
a table search access.
In the single entry mode, the bus controller loads a single long-word entry
mode operation is not requested by the MC68030 or is not supported by
of the responding device is smaller than 32 bits, the MC68030 executes all
bus cycles necessary to fill the long word.
size of the transfer, the responding device must consistently assert the cache
inhibit input (CIIN) signal. For example, a 32-bit port must always supply 32
bits, even for 8- and 16-bit transfers; a 16-bit port must supply 16 bits, even
signal indicates that all 16 bits are valid. If the device cannot supply its full
port width of data, it must assert CIIN for all bus cycles corresponding to a
cache entry.
bits are requested. Similarly, the processor assumes that a 16-bit termination
C a c h e
READ-MODIFY-WRITE ACCESSES.
• Single entry mode
• Burst fill mode
F i l l i n g
MC68030 USER'S MANUAL
When a cachable access is initiated and a burst
The read portion of a read-modify-write
MOTOROLA