MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 303

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9
9-2
the MMU to the execution unit and the bus controller. For an instruction or
caches on a read cycle, the bus controller aborts the bus cycle before address
the assertion of address strobe when a valid translation is not available in
the ATC or when an invalid access is attempted.
An MMU disable input signal ([VlMUDIS) is provided that dynamically disables
The programming model of the MMU (see Figure 9-2) consists of two root
visor mappings. The translation control register is comprised of fields that
formation from a translation performed as a part of a PTEST instruction.
The MMU completely overlaps address translation time with other processing
activity when the translation is resident in the ATC. ATC accesses operate in
operand access, the MC68030 simultaneously searches the caches and
searches for a physical address in the ATC. If the translation is available, the
cycle to continue. When the instruction or operand is in either of the on-chip
strobe is asserted. Similarly, the MMU causes a bus cycle to abort before
address translation for emulation, diagnostic, or other purposes.
pointer registers, a control register, two transparent translation registers, and
a status register. These registers can only be accessed by supervisor pro-
grams. The CPU root pointer register points to an address translation tree
structure in memory that describes the logical-to-physical mapping for user
accesses or for both user and supervisor accesses. The supervisor root pointer
control the translation operation. Each transparent translation register can
define a block of logical addresses that are used as physical addresses (with-
out translation). The MMU status register contains accumulated status in-
parallel with the on-chip instruction and data caches.
Figure 9-1 is a block diagram of the MC68030 showing the relationship of
MMU provides the physical address to the bus controller and allows the bus
register optionally points to an address translation tree structure for super-
• External Translation Disable Input Signal (MMUDIS)
• Subset of Instruction Set Defined by MC68851
•
• Portions of Tables Can Be Undefined (Using Limits)
• Write Protection and Supervisor Protection
• History Bits Automatically Maintained in Page Descriptors
• Cache Inhibit Output (CLOUT) Signal Asserted on Page Basis
0-15 Upper Logical Address Bits Can Be Ignored (Using Initial Shift)
MC68030 USER'S MANUAL
MOTOROLA