MPC8555ECPXAJD Freescale Semiconductor, MPC8555ECPXAJD Datasheet - Page 25

• Manufacturer Part Number: MPC8555ECPXAJD
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8555ECPXAJD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8555CDS - BOARD EVALUATION CDS FOR 8555CWH-PPC-8555N-VX - BOARD EVAL QUICCSTART MPC8555CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540CWH-PPC-8555N-VE - EVALUATION SYSTEM QUICC MPC8555E
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

8.2.2.1
Table 21
Figure 8
Figure 9
Freescale Semiconductor
At recommended operating conditions with LV
RX_CLK clock period
RX_CLK duty cycle
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise and fall time
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
(reference)(state)
symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to
the t
with respect to the time data input signals (D) went invalid (X) relative to the t
state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing
the clock of a particular functional. For example, the subscript of t
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
RX
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides the AC test load for TSEC.
shows the GMII receive AC timing diagram.
provides the GMII receive AC timing specifications.
clock reference (K) going to the high state (H) or setup time. Also, t
GMII Receive AC Timing Specifications
for inputs and t
Parameter/Condition
RXD[7:0]
RX_CLK
RX_DV
RX_ER
Output
(first two letters of functional block)(reference)(state)(signal)(state)
Table 21. GMII Receive AC Timing Specifications
Figure 9. GMII Receive AC Timing Diagram
t
t
GRXH
GRDVKH
DD
of 3.3 V ± 5%.
Figure 8. TSEC AC Test Load
t
GRX
Z
0
= 50 Ω
t
GRXR
t
Symbol
GRXH
t
t
GRDXKH
GRDVKH
t
GRXF
t
, t
GRX
GRXF
/t
GRX
t
GRX
GRDXKH
1
represents the GMII (G) receive (RX) clock. For rise
2,3
(first two letters of functional block)(signal)(state)
R
GRDXKL
L
t
GRXR
= 50 Ω
GRX
Min
2.0
0.5
—
40
—
clock reference (K) going to the low (L)
symbolizes GMII receive timing (GR)
for outputs. For example, t
Ethernet: Three-Speed, MII Management
LV
DD
Typ
8.0
—
—
—
—
/2
Max
1.0
60
—
—
—
GRDVKH
Unit
ns
ns
ns
ns
%
25