MPC8555ECPXAJD Freescale Semiconductor, MPC8555ECPXAJD Datasheet - Page 29

• Manufacturer Part Number: MPC8555ECPXAJD
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8555ECPXAJD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8555CDS - BOARD EVALUATION CDS FOR 8555CWH-PPC-8555N-VX - BOARD EVAL QUICCSTART MPC8555CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540CWH-PPC-8555N-VE - EVALUATION SYSTEM QUICC MPC8555E
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

8.2.4.2
Table 25
Figure 13
Freescale Semiconductor
At recommended operating conditions with LV
RX_CLK clock period
RX_CLK skew
RX_CLK duty cycle
RCG[9:0] setup time to rising RX_CLK
RCG[9:0] hold time to rising RX_CLK
RX_CLK clock rise time and fall time
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. Guaranteed by design.
(reference)(state)
symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the
t
respect to the time data input signals (D) went invalid (X) relative to the t
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of t
the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is
skew (SK) followed by the clock that is being skewed (TRX).
TRX
clock reference (K) going to the high (H) state or setup time. Also, t
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides the TBI receive AC timing specifications.
shows the TBI receive AC timing diagram.
TBI Receive AC Timing Specifications
Parameter/Condition
for inputs and t
RX_CLK1
RX_CLK0
RXD[9:0]
(first two letters of functional block)(reference)(state)(signal)(state)
Table 25. TBI Receive AC Timing Specifications
Figure 13. TBI Receive AC Timing Diagram
DD
t
SKTRX
t
TRXH
of 3.3 V ± 5%.
t
TRDVKH
t
TRX
t
TRX
TRXH
represents the TBI (T) receive (RX) clock. For rise and fall times,
Valid Data
t
TRXR
t
Symbol
TRXH
t
t
TRDXKH
t
TRDVKH
SKTRX
t
, t
TRX
TRXF
/t
t
TRX
TRXF
1
2,3
(first two letters of functional block)(signal)(state)
TRX
Valid Data
TRDXKH
t
TRDXKH
clock reference (K) going to the high (H) state.
Min
7.5
2.5
1.5
0.7
40
t
TRXR
symbolizes TBI receive timing (TR) with
t
TRDVKH
for outputs. For example, t
Ethernet: Three-Speed, MII Management
t
TRDXKH
16.0
Typ
—
—
—
—
—
Max
8.5
2.4
60
—
—
TRDVKH
Unit
ns
ns
ns
ns
ns
%
29