MPC8540PX667LC Freescale Semiconductor, MPC8540PX667LC Datasheet - Page 17

• Manufacturer Part Number: MPC8540PX667LC
• Description: IC MPU 32BIT 667MHZ 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8540PX667LC

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548MPC8540ADS-BGA - BOARD APPLICATION DEV 8540CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3.19 OCeaN Switch Fabric
In order to reduce the strain on the core interconnects with the addition of new functional blocks in this generation
of the PowerQUICC family, an on-chip non-blocking crossbar switch fabric called OCeaN (on-chip network) has
been integrated to decrease contention, decrease latency, and increase bandwidth. This revolutionary non-blocking
crossbar fabric allows for full-duplex port connections at 128 Gbps concurrent throughput and independent per-port
transaction queuing and flow control.
3.20 Processing Across the On-Chip Fabric
When processing across the on-chip fabric, the ATMUs at each fabric port are used to determine the flow of data
across the MPC8540. The ATMUs at each fabric port are responsible for generating a fabric port destination ID as
well as a new local device address. The port ID and local address are based on the programmed destination of the
transaction. The following is a general overview of how the ATMUs process transactions over the on-chip fabric.
(Refer to
3.21 Data Processing with the e500 Coherency Module
Processing through the ECM is similar to processing across the on-chip fabric (in the sense of how data is received
and transmitted) with the exception that the transaction passes through the ECM. The purpose of the ECM is to
provide a means for any I/O transaction to maintain coherency with the cacheable DDR SDRAM and the local bus
memory. However, simply using the ECM does not make transactions across it coherent. The e500 and L2 cache are
snooped to maintain coherency only if the transaction across the ECM is designated as global (GBL bit set).
Otherwise, the transaction passes through the ECM using the ECM as a simple conduit to get to its destination. In
essence, only global transactions across the ECM are coherent transactions; all other transaction (across the on-chip
fabric) are non-coherent.
4 MPC8540 Application Examples
The following section provides block diagrams of different MPC8540 applications. The MPC8540 is a very flexible
device and can be configured to meet many system application needs. In order to build a system, many factors should
be considered.
Freescale Semiconductor
1. When a transaction on one of the fabric ports begins, the ATMU on the origination port translates the
2. The data is then processed across the on-chip fabric from the origination port to the destination port.
3. If the destination port connects off-chip (for example, to a PCI or RapidIO device), the local device address
programmed destination address into both a destination fabric port ID and a local device address.
is translated by the destination port ATMU to an outbound address with respect to the destination port’s
memory map, and the data is processed accordingly.
Figure
2.)
MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1
Figure 2. Processing Transactions Across the On-Chip Fabric
ATMU
1
2
ATMU
3
MPC8540 Application Examples
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