MPC8541EVTAQF Freescale Semiconductor, MPC8541EVTAQF Datasheet - Page 63

• Manufacturer Part Number: MPC8541EVTAQF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8541EVTAQF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Development Tools By Supplier: RDK-IDM-SBC
• Maximum Clock Frequency: 1000 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
PB[18:31]
PC[0, 1, 4–29]
PD[7, 14–25, 29–31]
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
2. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OV
3. This pin must always be pulled down to GND.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8541E is in
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or
8. The value of LALE and LGPL2 at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ pull-up
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
10. This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
11. This output is actively driven during reset rather than being three-stated during reset.
12. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13. These pins are connected to the V
14. Internal thermally sensitive resistor.
15. No connections should be made to these pins.
16. These pins are not connected for any functional use.
17. PCI specifications recommend that a weak pull-up resistor (2–10 kΩ) be placed on the higher order pins to OV
18. If this pin is connected to a device that pulls down during reset, an external pull-up is required to that is strong enough to
19. Recommend a pull-up resistor (~1 kΩ) be placed on this pin to OV
20. These are test signals for factory use only and must be pulled up (100Ω το 1kΩ) to OV
21. If this signal is used as both an input and an output, a weak pull-up (~10kΩ) is required on this pin.
22. MSYNC_IN and MSYNC_OUT should be connected together for proper operation.
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. If an
external device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is
intended to be high during reset.
pull-down resistors. See
or pull-down resistors. See the
because it has other manufacturing test functions. This pin therefore is described as an I/O for boundary scan.
operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
PCI device. Refer to the PCI Specification .
and regulation.
using 64-bit buffer mode (pins PCI_AD[63:32] and PCI2_C_BE[7:4]).
pull this signal to a logic 1 during reset.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Signal
Section 15.2, “Platform/System PLL
Y4, AA2, AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4,
P7, P6, P5, P4, P3, P2, P1, R1, R2, R3, R4, R5, R6,
R8, R9, T9, T6, T5, T4, T1, U1, U2, U3, U4, U7, U8,
U9, U10, V9, V6, V5, V4, V3, V2, V1, W1, W2, W3,
Table 43. MPC8541E Pinout Listing (continued)
Section 15.3, “e500 Core PLL
DD
/GND planes internally and may be used by the core power supply to improve tracking
AC3, AC2, AC1, AD6, AE3, AE2
Package Pin Number
W6, W7, W8
R7
Ratio.”
Ratio.”
DD
.
DD
.
Pin Type
DD
I/0
I/0
I/0
for normal machine operation.
Package and Pin Listings
Supply
Power
OV
OV
OV
DD
DD
DD
DD
when
Notes
—
—
—
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