MPC8560VT667LC Freescale Semiconductor, MPC8560VT667LC Datasheet

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... Freescale Semiconductor, Inc. Advance Information MPC8560PB Rev. 0, 12/2003 MPC8560 PowerQUICC III™ Integrated Communications Processor Product Brief The MPC8560 PowerQUICC III™ next-generation PowerQUICC II™ integrated communications processor. The MPC8560 integrates the processing power for networking and communications peripherals. resulting in higher device performance. The MPC8560 contains an embedded PowerPC™ ...

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... Freescale Semiconductor, Inc. Key Features Key Features Part II MPC8560 Overview The following section provides a high-level overview of the features of the MPC8560. Figure 1 shows the major functional units in the MPC8560. DDR DDR Memory Controller SDRAM Interface GPIO Local Bus Controller 32b Programmable Interrupt ...

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... Freescale Semiconductor, Inc. — The single-precision floating-point (SPFP) APU provides an instruction set for single-precision (32-bit) floating-point instructions. — Memory management unit (MMU) especially designed for embedded applications — Enhanced hardware and software debug support — Performance monitor facility (similar to but different from the MPC8560 performance monitor described in the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual ...

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... Freescale Semiconductor, Inc. Key Features Key Features — Time-slot assigner (TSA) supports multiplexing of data from any of the SCCs and FCCs onto eight time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following TDM formats: – T1/CEPT lines – T3/E3 – Pulse code modulation (PCM) highway interface – ...

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... Freescale Semiconductor, Inc. – Four outbound windows plus default translation for PCI – Eight outbound windows plus default translation for RapidIO • DDR memory controller — Programmable timing supporting DDR-1 SDRAM — 64-bit data interface 333-MHz data rate — Four banks of memory supported, each Gbyte — ...

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... Freescale Semiconductor, Inc. Key Features Key Features — Supports 4 message interrupts with 32-bit messages — Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller — Four global high resolution timers/counters that can generate interrupts — Supports 22 other internal interrupt sources — ...

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... Freescale Semiconductor, Inc. — 9.6-Kbyte jumbo frame support — RMON statistics support — 2-Kbyte internal transmit and receive FIFOs — MII management interface for control and status — Programmable CRC generation and checking — Ability to force allocation of header information and buffer descriptors into L2 cache • ...

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... Freescale Semiconductor, Inc. e500 Core Overview e500 Core Overview • System performance monitor — Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the 8 counters — ...

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... Freescale Semiconductor, Inc. The following is a brief list of some of the key features of the e500 core complex: • Implements full Book E 32-bit architecture • Implements additional instructions, registers, and interrupts defined by APUs. The SPE provides an extensive instruction set for 64-bit vector integer, single-precision floating-point, and fractional operations ...

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... Freescale Semiconductor, Inc. e500 Core Overview e500 Core Overview • Two simple execution units that perform the following: — Single-cycle add and subtract — Single-cycle shift and rotate — Single-cycle logical operations — Supports integer signal processing operations • Multiple-cycle execution unit (MU) — ...

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... Freescale Semiconductor, Inc. • Extended exception handling — Supports Book E interrupt model – Interrupt vector prefix register (IVPR) – Vector offset registers (IVORs) 0–15 as defined in Book E, plus e500-defined IVORs 32–35 – Exception syndrome register (ESR) – Book E–defined preempting critical interrupt, including critical interrupt status registers (CSRR0 and CSRR1) and an rfci instruction — ...

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... Freescale Semiconductor, Inc. Communications Processor Module (CPM) Communications Processor Module (CPM) • Reliability and serviceability — Internal code parity — Parity checking on e500 local bus 3.2 Communications Processor Module (CPM) The CPM contains features that allow the MPC8560 to excel in a variety of applications targeted for the networking and telecommunication markets ...

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... Freescale Semiconductor, Inc. activities. The CP has an instruction set optimized for communications but that can also be used for general-purpose applications, relieving the system core of small, often repeated tasks. • Two serial DMAs (SDMAs), one associated with the local bus and one associated with the e500 coherency module (ECM), handling transfers simultaneously • ...

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... Freescale Semiconductor, Inc. e500 Coherency Module (ECM) e500 Coherency Module (ECM) — Locks for the entire cache may be set and cleared by accesses to memory-mapped control registers 3.3.1 On-Chip Memory as Memory-Mapped SRAM When the on-chip memory is configured as an SRAM, the 256 Kbytes of memory can be configured to reside at any aligned location in the memory map ...

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... Freescale Semiconductor, Inc. memory. It also provides a flexible switch-type structure for core and I/O-initiated transactions to be routed or dispatched to target modules on the device. 3.5 DDR SDRAM Controller The MPC8560 supports DDR-I SDRAM that operates 166 MHz (333-MHz data rate). The memory interface controls main memory accesses and provides for a maximum of 3.5 Gbytes of main memory. The memory controller can be configured to support the various memory sizes through software initialization of on-chip configuration registers ...

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... Freescale Semiconductor, Inc. Boot Sequencer Boot Sequencer complex applications with multiprocessor control. The I a clocking unit, and a control unit. The I rejects spikes on the bus. 3.8 Boot Sequencer The MPC8560 provides a boot sequencer that uses the I loads the data into the MPC8560’s configuration registers. The boot sequencer is enabled by a configuration pin sampled at the negation of the MPC8560 hardware reset signal ...

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... Freescale Semiconductor, Inc. The MPC8560 TSECs support programmable CRC generation and checking, RMON statistics, and jumbo frames 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache to speed classification or other frame processing. 3.11 Integrated DMA The MPC8560 DMA engine is capable of transferring blocks of data from any legal address range to any other legal address range ...

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... Freescale Semiconductor, Inc. Power Management Power Management The RapidIO unit on the MPC8560 supports the I/O and message-passing logical specifications, the common transport specification, and the 8/16 LP-LVDS physical layer specification of the RapidIO Interconnect Specification. It does not support the globally shared memory logical specification. ...

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... Freescale Semiconductor, Inc. 3.16 Address Map The MPC8560 supports a flexible physical address map. Conceptually, the address map consists of local space and external address space. The local address map is 4 Gbytes. The MPC8560 can be made part of a larger system address space through the mapping of translation windows. This functionality is included in the address translation and mapping units (ATMUs) ...

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... Freescale Semiconductor, Inc. Processing Across the On-Chip Fabric Processing Across the On-Chip Fabric Because FIFOs are typically smaller than the incoming PDU, steps 1–3 may be repeated several times to store the entire packet. There may also be times when the incoming PDU is larger than the buffer length defined in the RxBD. In such cases, steps 4– ...

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... Freescale Semiconductor, Inc. programmed destination of the transaction. The following is a general overview of how the ATMUs process transactions over the on-chip fabric. (Refer to Figure 4.) 1. When a transaction on one of the fabric ports begins, the ATMU on the origination port translates the programmed destination address into both a destination fabric port ID and a local device address ...

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... Freescale Semiconductor, Inc. Device Configurations Device Configurations Part V MPC8560 Application Examples The following section provides block diagrams of different MPC8560 applications. The MPC8560 is a very flexible device and can be configured to meet many system application needs. In order to build a system, many factors should be considered. ...

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... Freescale Semiconductor, Inc. 5.1.2 Multiprocessor System Figure 6 shows a multiprocessor system configuration. PHY MII/GMII/RGMII Transceiver 155-Mbps ATM PHY PHY MII/GMII/RGMII Transceiver 155-Mbps ATM PHY Figure 6. High-Performance Communications This system enhances the serial throughput by connecting one MPC8560 to another MPC8560 with the RapidIO interface. The core in one of the MPC8560 devices can easily access the data stored in the DDR SDRAM memory of the other MPC8560 ...

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... Freescale Semiconductor, Inc. Examples of Communications Systems Examples of Communications Systems 5.1.3 High-Performance System Figure 7 shows a configuration with a high-performance system. PHY MII/GMII/RGMII Transceiver 155-Mbps ATM PHY Figure 7. High-Performance System Microprocessor Configuration In this system, an external high-performance microprocessor is connected to the MPC8560 through the RapidIO bus to share the processing load of the e500 core between the MPC8560 and the external processor in order to increase higher layer processing ...

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... Freescale Semiconductor, Inc. 5.2.1 Remote Access Server Figure 8 shows a remote access server configuration. Quad T1 Framer and Framer or 155-Mbps ATM PHY or MII/GMII/RGMII Transceiver Slow Comm PHY Figure 8. Remote Access Server Configuration In this application, eight TDM ports are connected to external framers. In the MPC8560, each group of four ports supports up to 128 channels. One TDM interface can support 32– ...

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... Freescale Semiconductor, Inc. Examples of Communications Systems Examples of Communications Systems The local bus can be used as an interface to a bank of DSPs that can perform analog modem signal modulation. Data to and from the DSPs can be transferred through the MPC8560 DMA controller. The MPC8560 local bus memory controller supports pipeline SDRAM devices for efficient burst transfers. ...

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... Freescale Semiconductor, Inc. 5.2.3 LAN-to-WAN Bridge Router Figure 10 shows a LAN-to-WAN router configuration, which is similar to the previous example. MII/GMII/RGMII Transceiver 155-Mbps ATM PHY 155-Mbps ATM PHY Slow Comm PHY Figure 10. LAN-to-WAN Bridge Router Configuration MOTOROLA Integrated Communications Processor Product Brief For More Information On This Product, PRELIMINARY— ...

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... Freescale Semiconductor, Inc. Examples of Communications Systems Examples of Communications Systems 5.2.4 Cellular Base Station Figure 11 shows a cellular base station configuration. Quad Framer MII/GMII/RGMII Transceiver Slow Comm PHY Figure 11. Cellular Base Station Configuration Here the MPC8560 channelizes 8 E1s (up to 256 64-Kbps channels). The local bus can control a bank of DSPs ...

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... Freescale Semiconductor, Inc. 5.2.5 3G Wireless Base Station Figure 12 shows a 3G wireless base station configuration. T3/E3 Framer To Backplane MII/GMII/RGMII Transceiver Slow Comm PHY Figure 12. 3G Wireless Base Station Configuration Here the MPC8560 uses two E3/T3s for ATM connections, or alternatively, two high-bit rate HDLC connections ...

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... Freescale Semiconductor, Inc. Examples of Communications Systems Examples of Communications Systems 5.2.6 Telecommunications Switch Controller Figure 13 shows a telecommunications switch controller configuration. 155-Mbps ATM PHY MII/GMII/RGMII Transceiver Slow Comm PHY Figure 13. Telecommunications Switch Controller Configuration The MPC8560 CPM supports a total aggregate throughput of 1 Gbps at 333 MHz. This includes one full-duplex, 155-Mbps ATM channel ...

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... Freescale Semiconductor, Inc. 5.2.7 SONET Transmission Controller Figure 14 shows a SONET transmission controller configuration. To ASIC Payload 576 Kbps SONET/STM Overhead Framer Channel 192 Kbps MII/GMII/RGMII Transceiver Slow Comm PHY Figure 14. SONET Transmission Controller Configuration In this application, the MPC8560 implements super channeling with the MCC. Nine 64-Kbps channels are aggregated to form a 576-Kbps channel ...

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... Freescale Semiconductor, Inc. Examples of Communications Systems Examples of Communications Systems 5.2.8 Frame Relay Card Figure 15 shows a frame relay card configuration. Quad Framer MII Transceiver Figure 15. Frame Relay Card Configuration 5.2.9 ATM Protocol Converter Figure 16 shows an ATM protocol converter. 155-Mbps ATM PHY MII Transceiver Figure 16 ...

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... Freescale Semiconductor, Inc. In this configuration, the MPC8560 can convert traffic from ATM to Ethernet and from Ethernet to ATM. The MPC8560 is also connected to a redundant gigabit Ethernet switch fabric backplane THROUGH the two TSECs. Part VI Compatibility Issues This section describes some software and hardware compatibility issues. ...

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... Freescale Semiconductor, Inc. MPC8560 Configurations MPC8560 Configurations Table 1. MPC8560 Protocols (continued) Protocol TSEC √ 100BaseT √ 10BaseT HDLC HDLC_BUS Transparent UART Multichannel 6.5 MPC8560 Configurations The MPC8560 offers flexibility in configuring the device for specific applications. The functions mentioned in the above sections are all available in the device, but not all of them can be used at the same time. This does not imply that the device is not fully activated in any given implementation ...

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... Freescale Semiconductor, Inc. Table 2. MPC8560 Serial Performance Protocol Ethernet FCC: 100BaseT HDLC MCC: HDLC No Bus Limitation FCC: AAL5 Connection Tables on Local Bus ATM No Bus Limitation FCC: AAL0 Connection Tables on Local Bus FCC: AAL2 CPS These performance estimates assume the CPM is operating at 333 MHz, and that data is stored in SDRAM on the local bus operating at 166 MHz ...

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... HOME PAGE: www.motorola.com/semiconductors Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...