MC68020CRC16E Freescale Semiconductor, MC68020CRC16E Datasheet - Page 80

• Manufacturer Part Number: MC68020CRC16E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020CRC16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.3.2 Write Cycle
During a write cycle, the processor transfers data to memory or a peripheral device.
Figure 5-24 is a flowchart of a write cycle operation for a long-word transfer. Figures 5-25–
5-28 are write cycle timing diagrams in terms of clock periods. Figure 5-25 shows two
write cycles (between two read cycles with no idle time in between) for a 32-bit port.
Figure 5-26 shows byte and word write cycles to a 32-bit port. Figure 5-27 shows a long-
word write cycle to an 8-bit port. Figure 5-28 shows a long-word write cycle to a 16-bit
port.
MOTOROLA
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*
*
*
*
This step does not apply to the MC68EC020.
For the MC68EC020, A23–A0.
1) ASSERT ECS/OCS FOR ONE-HALF CLOCK
2) DRIVE ADDRESS ON A31–A0
3) DRIVE FUNCTION CODES ON FC2–FC0
4) DRIVE SIZ1, SIZ0 (FOUR BYTES)
5) SET R/W TO WRITE
6) ASSERT AS
7) ASSERT DBEN
8) DRIVE DATA LINES D31–D0
9) ASSERT DS
1) NEGATE AS AND DS
2) REMOVE DATA FROM D31–D0
3) NEGATE DBEN
TERMINATE OUTPUT TRANSFER
START NEXT CYCLE
ADDRESS DEVICE
PROCESSOR
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 5-24. Write Cycle Flowchart
Go to: www.freescale.com
M68020 USER’S MANUAL
1) DECODE ADDRESS
2) STORE DATA FROM D31–D0
3) ASSERT DSACK1/DSACK0
1) NEGATE DSACK1/DSACK0
EXTERNAL DEVICE
TERMINATE CYCLE
ACCEPT DATA
5- 33