MC68LC060ZU50 Freescale Semiconductor, MC68LC060ZU50 Datasheet - Page 101

• Manufacturer Part Number: MC68LC060ZU50
• Description: IC MPU 32BIT 68K 50MHZ 304-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060ZU50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 304-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Caches
bit for the line. Note that only the data cache supports dirty cache lines. Figure 5-2 illustrates
the instruction cache line format and Figure 5-3 illustrates the data cache line format.
The cache stores an entire line, providing validity on a line-by-line basis. Only burst mode
accesses that successfully read four long words can be cached.
A cache line is always in one of three states: invalid, valid, or dirty. For invalid lines, the V-
bit is clear, causing the cache line to be ignored during lookups. Valid lines have their V-bit
set and D-bit cleared, the line contains valid data consistent with memory. Dirty cache lines
5-2
EXECUTION UNIT
EXECUTE
FETCH
FLOATING-
EA
FP
POINT
UNIT
OC
EX
BRANCH
CACHE
WHERE:
TAG—21-BIT PHYSICAL ADDRESS TAG
V—VALID BIT FOR LINE
D—DIRTY BIT FOR LINE
LWn—LONG WORD n (32-BIT) DATA ENTRY
pOEP
DATA AVAILABLE
WHERE:
TAG—21-BIT PHYSICAL ADDRESS TAG
V—VALID BIT FOR LINE
LWn—LONG WORD n (32-BIT) DATA ENTRY
CALCULATE
EXECUTE
WRITE-BACK
DECODE
FETCH
INT
EA
EA
Figure 5-1. MC68060 Instruction and Data Caches
TAG
TAG
INSTRUCTION FETCH UNIT
INSTRUCTION
Figure 5-2. Instruction Cache Line Format
INTEGER UNIT
BUFFER
OC
DS
AG
EX
Figure 5-3. Data Cache Line Format
V D
sOEP
V
CALCULATE
DECODE
EXECUTE
INSTRUCTION
FETCH
CALCULATE
EA
INT
DECODE
EA
FETCH
EARLY
IA
M68060 USER’S MANUAL
LW3
LW3
OPERAND DATA BUS
AG
DS
OC
EX
IB
IAG
IED
IC
WB
DA
LW2
LW2
INSTRUCTION
INSTRUCTION MEMORY UNIT
DATA
ATC
ATC
DATA MEMORY UNIT
INSTRUCTION
CONTROLLER
CONTROLLER
CACHE
CACHE
LW1
DATA
LW1
INSTRUCTION
CACHE
CACHE
DATA
LW0
LW0
U
C
O
N
R
O
R
B
S
T
L
L
E
MOTOROLA
CONTROL
ADDRESS
DATA