MC68LC060ZU50 Freescale Semiconductor, MC68LC060ZU50 Datasheet - Page 320

• Manufacturer Part Number: MC68LC060ZU50
• Description: IC MPU 32BIT 68K 50MHZ 304-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060ZU50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 304-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

FABS
FDABS
FSABS
FADD
FDADD
FSADD
FCMP
FDIV
FDDIV
FSDIV
FMOVE
,FPx
FDMOVE
,FPx
FSMOVE
,FPx
FMOVE
FPy,
FMOVE
,FPCR
FMOVE
FPCR,
FINT
FINTRZ
Instruction
Instruction Execution Timing
10.15 FPU INSTRUCTION EXECUTION TIMES
Table 10-25 shows the number of clock cycles required for execution of the floating-point
instructions, including completion of the operation and storing of the result. The number of
operand read and write cycles is shown in parentheses (r/w).
10-24
1
2
PLPA (ATC hit)
PLPA (ATC miss)
PFLUSH
PFLUSHN
PFLUSHAN
PFLUSHA
RESET
STOP
SWAP
TRAPF
TRAPcc
TRAPV
UNLK
UNPK
For these entries, add the effective address calculation time.
For the CPUSH instruction, the operand write figure refers to line-sized transfers.
Table 10-24. Miscellaneous Instruction Execution Times (Continued)
37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0)
37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0)
37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
3(0/0)
3(0/0)
3(0/0)
1(0/0)
3(0/0)
3(0/0)
FPn
—
—
—
Instruction
Table 10-25. Floating-Point Instruction Execution Times
3(0/0)
3(0/0)
3(0/0)
5(0/0)
5(0/0)
5(0/0)
3(0/0)
3(0/0)
3(0/0)
3(0/0)
3(0/0)
8(0/0)
4(0/0)
4(0/0)
4(0/0)
Dn
1(1/0)
1(1/0)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(0/1)
6(1/0)
2(0/1)
3(1/0)
3(1/0)
(An)
Word
Word
(An)+
1(1/0)
1(1/0)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(0/1)
6(1/0)
2(0/1)
3(1/0)
3(1/0)
Size
—
—
—
—
—
—
—
—
—
—
—
—
M68060 USER’S MANUAL
Register
520(0/0)
15(0/0)
28(0/0)
18(0/0)
18(0/0)
33(0/0)
33(0/0)
8(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(1/0)
2(0/0)
1(1/0)
1(1/0)
3(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(0/1)
6(1/0)
2(0/1)
3(1/0)
–(An)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
Effective Address, <ea>
(d16,An)
(d16,PC)
37(1/0)
37(1/0)
37(1/0)
1(1/0)
1(1/0)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
6(1/0)
2(1/0)
3(1/0)
3(1/0)
Memory
2(1/1)
—
—
—
—
—
—
—
—
—
—
—
—
—
(d8,PC,Xi SF)
(d8,An,Xi SF)
38(1/0)
38(1/0)
38(1/0)
2(0/1)
7(1/0)
3(0/1)
2(1/0)
2(1/0)
2(1/0)
4(1/0)
4(1/0)
4(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
3(1/0)
Reg -> Dest
—
—
—
—
—
—
(bd,PC,XI SF)
—
—
—
—
—
—
—
—
(bd,An,XI SF)
39(1/0)
39(1/0)
39(1/0)
3(1/0)
3(1/0)
3(1/0)
3(0/1)
8(1/0)
4(0/1)
3(1/0)
3(1/0)
3(1/0)
5(1/0)
5(1/0)
5(1/0)
3(1/0)
5(1/0)
5(1/0)
Source -> Reg
(xxx).WL #<imm>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
38(1/0)
38(1/0)
38(1/0)
2(0/1)
7(1/0)
3(0/1)
2(1/0)
2(1/0)
2(1/0)
4(1/0)
4(1/0)
4(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
3(1/0)
MOTOROLA
38(0/0)
38(0/0)
38(0/0)
1(0/0)
1(0/0)
1(0/0)
7(0/0)
2(0/0)
2(0/0)
2(0/0)
4(0/0)
4(0/0)
4(0/0)
2(0/0)
3(0/0)
3(0/0)
—
—