MC68LC060ZU50 Freescale Semiconductor, MC68LC060ZU50 Datasheet - Page 130

• Manufacturer Part Number: MC68LC060ZU50
• Description: IC MPU 32BIT 68K 50MHZ 304-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060ZU50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 304-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Floating-Point Unit
The FPU performs all floating-point internal operations in extended precision. It supports
mixed-mode arithmetic by converting single- and double-precision operands to extended-
precision values before performing the specified operation. The FPU converts all memory
data formats to extended precision before using it in a floating-point operation or loading it
in a floating-point data register. The FPU also converts extended-precision data formats in
a floating-point data register to any data format and either stores it in a memory destination
or in an integer data register.
If the external operand is a denormalized number or unnormalized number, the number is
normalized before an operation is performed. However, an external denormalized number
moved into a floating-point data register is stored as a denormalized number.
If an external operand is an unnormalized number, the number is normalized before it is
used in an arithmetic operation. If the external operand is an unnormalized zero (i.e., with a
mantissa of all zeros), the number is converted to a normalized zero before the specified
operation is performed. The regular use of unnormalized inputs not only defeats the purpose
of the IEEE 754 standard, but also can produce gross inaccuracies in the results.
6.3.1 Intermediate Result
Figure 6-8 illustrates the intermediate result format. The intermediate result’s exponent for
some dyadic operations (e.g., multiply and divide) can easily overflow or underflow the 15-
bit exponent of the destination floating-point register. To simplify the overflow and underflow
detection, intermediate results in the FPU maintain a 16-bit, twos-complement integer expo-
nent. Detection of an overflow or underflow intermediate result always converts the 16-bit
exponent into a 15-bit biased exponent before being stored in a floating-point data register.
The FPU internally maintains the 67-bit mantissa for rounding purposes. The mantissa is
always rounded to 64 bits (or less, depending on the selected rounding precision) before it
is stored in a floating-point data register.
If the destination is a floating-point data register, the result is in the extended-precision for-
mat and is rounded to the precision specified by the FPCR PREC bits before being stored.
All mantissa bits beyond the selected precision are zero. If the single- or double-precision
mode is selected, the exponent value is in the correct range even if it is stored in extended-
precision format. If the destination is a memory location, the FPCR PREC bits are ignored.
In this case, a number in the extended-precision format is taken from the source floating-
point data register, rounded to the destination format precision, and then written to memory.
6-12
16-BIT EXPONENT
Figure 6-8. Intermediate Result Format
M68060 USER’S MANUAL
INTEGER BIT
OVERFLOW BIT
63-BIT FRACTION
LSB OF FRACTION
ROUND BIT
GUARD BIT
STICKY BIT
MOTOROLA