PCX745BVZFU350LE Atmel, PCX745BVZFU350LE Datasheet - Page 35

• Manufacturer Part Number: PCX745BVZFU350LE
• Description: IC MPU 32BIT 350MHZ 255PBGA
• Manufacturer: Atmel

Specifications of PCX745BVZFU350LE

• Processor Type: PowerPC 32-Bit RISC
• Speed: 350MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 255-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

8.2.2.1
2138G–HIREL–05/06
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is
optional in the IEEE 1149.1 specification, but is provided on all processors that implement the
PowerPC architecture. While it is possible to force the TAP controller to the reset state using
only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the
TRST signal is asserted during power-on reset. Because the JTAG interface is also used for
accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not
practical.
The COP function of these processors allows a remote computer system (typically, a PC with
dedicated hardware and debugging software) to access and control the internal operations of
the processor. The COP interface connects primarily through the JTAG port of the processor,
with some additional status monitoring signals. The COP port requires the ability to indepen-
dently assert HRESET or TRST in order to fully control the processor. If the target system has
independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, then the COP reset signals must bemerged into these signals with logic.
The arrangement shown in
HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG inter-
face and COP header will not be used, TRST should be tied to HRESET through a 0Ω isolation
resistor so that it is asserted when the systemreset signal (HRESET) is asserted ensuring that
the JTAG scan chain is initialized during power-on. While Freescale recommends that the COP
header be designed into the system as shown in
resistor will allow future access to TRST in the case where a JTAG interfacemay need to be
wired onto the system in debug situations.
The COP header shown in
and memory examination/modification, and other standard debugger features are possible
through this interface — and can be as inexpensive as an unpopulated footprint for a header to
be added when needed.
The COP interface has a standard header for connection to the target system, based on the
0.025" square-post 0.100" centered header assembly (often called a Berg header). The connec-
tor typically has pin 14 removed as a connector key.
Figure 8-14
Figure 8-14 on page 36
adds many benefits — breakpoints, watchpoints, register
Figure
allows the COP port to independently assert
8-14, if this is not possible, the isolation
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