PCX755BVZFU300LE Atmel, PCX755BVZFU300LE Datasheet - Page 39

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PCX755BVZFU300LE

Manufacturer Part Number
PCX755BVZFU300LE
Description
IC MPU 32BIT 300MHZ 360PBGA
Manufacturer
Atmel
Datasheet

Specifications of PCX755BVZFU300LE

Processor Type
PowerPC 32-Bit RISC
Speed
300MHz
Voltage
2V
Mounting Type
Surface Mount
Package / Case
360-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCX755BVZFU300LE
Manufacturer:
Atmel
Quantity:
10 000
9.4
Table 9-1.
Notes:
2138G–HIREL–05/06
PLL_CFG [0-3]
0100
1000
1110
1010
0111
1011
1001
1101
0101
0010
0001
1100
0110
0011
1111
Clock Relationship Choices
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode
4. In PLL off mode, no clocking occurs inside the PC755 regardless of the SYSCLK input.
frequencies which are not useful, not supported, or not tested for by the PC755; see
for valid SYSCLK, core, and VCO frequencies.
is set for 1:1 mode operation. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
PC755 Microprocessor PLL Configuration
Bus-to-Core
Multiplier
3.5x
4.5x
5.5x
6.5x
7.5x
10x
2x
3x
4x
5x
6x
7x
8x
PLL off/bypass
The PC755’s PLL is configured by the PLL_CFG[0-3] signals. For a given SYSCLK (bus) fre-
quency, the PLL configuration signals set the internal CPU and VCO frequency of operation.
The PLL configuration for the PC755 is shown in
frequencies.
PLL off
Core-to VCO
Multiplier
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
Bus 33
(400)
(433)
(466)
(500)
(533)
(666)
MHz
200
216
233
250
266
333
-
-
-
-
-
-
-
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
Bus 50
(400)
(450)
(500)
(550)
(600)
(650)
(700)
(750)
(800)
MHz
200
225
250
275
300
325
350
375
400
-
-
-
-
PLL off, no core clocking occurs
Bus 66
5733°
(400)
(466)
(533)
(600)
(666)
(800)
MHz
200
233
266
300
333
366
400
-
-
-
-
-
-
Figure 10-2 on page 41
“Clock AC Specifications” on page 25
Bus 75
(450)
(525)
(600)
(675)
(750)
MHz
225
263
300
338
375
-
-
-
-
-
-
-
-
Bus 80
(480)
(560)
(640)
(720)
(800)
MHz
240
280
320
360
400
PC755/745
-
-
-
-
-
-
-
-
for example
Bus 100
(400)
(600)
(700)
(800)
MHz
200
300
350
400
-
-
-
-
-
-
-
-
-
39

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