PCX755BVZFU300LE Atmel, PCX755BVZFU300LE Datasheet - Page 44

• Manufacturer Part Number: PCX755BVZFU300LE
• Description: IC MPU 32BIT 300MHZ 360PBGA
• Manufacturer: Atmel

Specifications of PCX755BVZFU300LE

• Processor Type: PowerPC 32-Bit RISC
• Speed: 300MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 360-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

10.6
44
Pull-up Resistor Requirements
PC755/745
Table 10-1
acterized at 0°C, 65°C, and 105°C. The impedance increases with junction temperature and is
relatively unaffected by bus voltage.
Table 10-1.
The PC755 requires pull-up resistors (1 kΩ – 5 kΩ) on several control pins of the bus interface to
maintain the control signals in the negated state after they have been actively negated and
released by the processor or other bus masters. These pins are TS, ABB, AACK, ARTRY, DBB,
DBWO, TA, TEA, and DBDIS. DRTRY should also be connected to a pull-up resistor (1 kΩ – 5
kΩ) if it will be used by the system; otherwise, this signal should be connected to HRESET to
select NO-DRTRY mode.
Three test pins also require pull-up resistors (100Ω – 1 kΩ). These pins are L1_TSTCLK,
L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be pulled up to
OV
In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 kΩ – 5
kΩ) if it is used by the system.
During inactive periods on the bus, the address and transfer attributes may not be driven by any
master and may, therefore, float in the high-impedance state for relatively long periods of time.
Since the processor must continually monitor these signals for snooping, this float condition may
cause additional power draw by the input receivers on the processor or by other receivers in the
system. These signals can be pulled up through weak (10 kΩ) pull-up resistors by the system or
may be otherwise driven by the system during inactive periods of the bus to avoid this additional
power draw, but address bus pull-up resistors are not necessary for proper device operation.
The snooped address and transfer attribute inputs are:
A[0:31], AP[0:3], TT[0:4], TBST, and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and,
therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system,
however, may require pull-ups, or that those signals be otherwise driven by the system during
inactive periods by the system. The data bus signals are: DH[0:31], DL[0:31], and DP[0:7].
If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be
disabled, and their outputs will drive logic zeros when they would otherwise normally be driven.
For this mode, these pins do not require pull-up resistors, and should be left unconnected by the
system to minimize possible output switching.
If address or data parity is not used by the system, and the respective parity checking is disabled
through HID0, the input receivers for those pins are disabled, and those pins do not require pull-
up resistors and should be left unconnected by the system. If all parity generation is disabled
through HID0, then all parity checking should also be disabled through HID0, and all parity pins
may be left unconnected by the system.
DD
Impedance
for normal machine operation.
RN
RP
summarizes the signal impedance results. The driver impedance values were char-
Impedance Characteristics. V
Processor bus
25-36
26-39
DD
L2 bus
25-36
26-39
= 2.0V, OV
DD
= 3.3V, T
Symbol
Z
Z
0
0
c
= 0 - 105°C
2138G–HIREL–05/06
Unit
W
W