N80960SB16 Intel, N80960SB16 Datasheet - Page 10

• Manufacturer Part Number: N80960SB16
• Description: IC MPU I960SB 16MHZ 84-PLCC
• Manufacturer: Intel

Specifications of N80960SB16

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: SB suffix, 32-Bit, 512 Byte Cache
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Other names: 803883

80960SB
1.1.7
In the 80960SB, floating-point arithmetic has been
made an integral part of the architecture. Having the
floating-point unit integrated on chip provides two
advantages. First, it improves the performance of the
chip
additional bus overhead is associated with floating-
point calculations, thereby leaving more time for
other bus operations such as I/O. Second, the cost of
using floating-point operations is reduced because a
separate coprocessor chip is not required.
The 80960SB floating-point (real-number) data types
include single-precision (32-bit), double-precision
(64-bit) and extended precision (80-bit) floating-point
numbers. Any registers may be used to execute
floating-point operations.
The processor provides hardware support for both
mandatory and recommended portions of IEEE
Standard 754 for floating-point arithmetic, including
all arithmetic, exponential, logarithmic and other
transcendental functions. Table 3 shows execution
times for some representative instructions.
1.1.8
The 80960SB CPU resides on a high-bandwidth
address/data bus. The bus provides a direct commu-
nication path between the processor and the
6
for
Floating-Point Arithmetic
High Bandwidth Bus
ONE OF FOUR
LOCAL
REGISTER SETS
floating-point
REGISTER
Figure 4. Multiple Register Sets Are Stored On-Chip
applications,
CACHE
since
no
31
memory
processor uses the bus to fetch instructions,
manipulate memory and respond to interrupts. Bus
features include:
•
•
•
Table 4 defines bus signal names and functions;
Table 5 defines other component-support signals
such as interrupt lines.
Table 3. Sample Floating-Point Execution Times
Add
Subtract
Multiply
Divide
Square Root
Arctangent
Exponent
Sine
Cosine
16-bit data path multiplexed onto the lower bits of
the 32-bit address path
Eight 16-bit half-word burst capability which
allows transfers from 1 to 16 bytes at a time
High bandwidth reads and writes with
25.6 MBytes/s burst (at 16 MHz)
Function
LOCAL REGISTER SET
and
I/O
( s) at 16 MHz
subsystem
32-Bit
15.8
17.7
23.8
23.8
0.6
0.6
1.1
2.0
5.8
0
r
r
0
interfaces.
15
64-Bit
20.5
19.5
25.9
25.9
0.8
0.8
2.0
4.5
6.1
The