N80960SB16 Intel, N80960SB16 Datasheet - Page 14

• Manufacturer Part Number: N80960SB16
• Description: IC MPU I960SB 16MHZ 84-PLCC
• Manufacturer: Intel

Specifications of N80960SB16

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: SB suffix, 32-Bit, 512 Byte Cache
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Other names: 803883

80960SB
10
RESET
INT0
INT1
INT2/INTR
INT3/INTA
NC
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
NAME
TYPE
T.S.
N/A
I/O
I
I
I
I
Table 5. 80960SB Pin Description: Support Signals
RESET clears the processor’s internal logic and causes it to reinitialize.
During RESET assertion, the input pins are ignored (except for INT0, INT1, INT3,
LOCK), the three-state output pins are placed in a HIGH impedance state (except
for DT/R, DEN, and AS) and other output pins are placed in their non-asserted
states.
RESET must be asserted for at least 41 CLK2 cycles for a predictable reset.
Optionally, for a synchronous reset, the LOW and HIGH transition of RESET
should occur after the rising edge of both CLK2 and the external bus CLK and
before the next rising edge of CLK2.
The interrupt pins indicate the initialization sequence executed. Typical initial-
ization requires driving only INT0 and INT3 to a HIGH state. The reset conditions
follow:
INT0
INTERRUPT 0 indicates a pending interrupt. To signal an interrupt in a
synchronous system, this pin — as well as the other interrupt pins — must be
enabled by being deasserted for at least one bus cycle and then asserted for at
least one additional bus cycle. In an asynchronous system, the pin must remain
deasserted for at least two system clock cycles and then asserted for at least two
more system clock cycles. The interrupt control register must be programmed with
an interrupt vector before using this pin.
INT0 is sampled during reset to determine if the self-test sequence is to be
executed.
INTERRUPT 1, like INT0, provides direct interrupt signaling. INT1 is sampled
during reset to determine if the self-test sequence is to be executed.
INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines
how this pin is interpreted. If INT2, it has the same interpretation as the INT0 and
INT1 pins. If INTR, it is used to receive an interrupt request from an external
interrupt controller.
INTERRUPT3/INTERRUPT ACKNOWLEDGE: The interrupt control register
determines how this pin is interpreted. If INT3, it has the same interpretation as
the INT0 and INT1 pins. If INTA, it is used as an output to control interrupt
acknowledge transactions. The INTA output is latched on-chip and remains valid
during T
reset.
NOT CONNECTED indicates pins should not be connected. Never connect any
pin marked NC; these pins may be reserved for factory use.
1
0
0
x
x
d
cycles; as an output, it is open-drain. INT3 must be pulled HIGH during
INT1
x
0
1
x
x
INT3
1
1
x
0
x
DESCRIPTION
LOCK
1
1
x
x
0
Run self test (core initialization)
Disable self-test
Reserved
Reserved
ONCE mode (see LOCK pin)
Action Taken