CS4299-JQZ Cirrus Logic Inc, CS4299-JQZ Datasheet - Page 29
![IC CODEC AC 97 W/SRC 48LQFP](/photos/6/80/68053/cs4299-jqz_sml.jpg)
CS4299-JQZ
Manufacturer Part Number
CS4299-JQZ
Description
IC CODEC AC 97 W/SRC 48LQFP
Manufacturer
Cirrus Logic Inc
Series
SoundFusion™r
Type
Audio Codec '97r
Datasheet
1.CS4299-JQZ.pdf
(52 pages)
Specifications of CS4299-JQZ
Package / Case
48-LQFP
Data Interface
Serial
Resolution (bits)
18 b, 20 b
Number Of Adcs / Dacs
1 / 1
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
85 / 87
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.3 V ~ 5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
8
Number Of Dac Outputs
3
Conversion Rate
48 KSPS
Interface Type
AC97
Resolution
18 bit, 20 bit
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Number Of Channels
1 ADC/1 DAC
Supply Current
10 mA
Thd Plus Noise
- 74 dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1044
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DS319PP6
4.16
SR[15:0]
Default
4.17
SR[15:0]
Default
SR15 SR14 SR13 SR12 SR11 SR10
SR15 SR14 SR13 SR12 SR11 SR10
D15
D15
PCM Front DAC Rate Register (Index 2Ch)
PCM L/R ADC Rate Register (Index 32h)
D14
D14
D13
D13
ed Audio Status/Control Register (Index 2Ah) is ‘set’. If the VRA bit is ‘clear’, all writes are ig-
nored and the register reads back BB80h; corresponding to a 48 kHz sample rate. If the VRA
bit is ‘set’, seven standard sample rates are available. If a sample rate written to the register is
not directly supported, the attempted value to be written will be decoded according to the ranges
indicated in Table 7. All register read transactions will reflect the actual value stored (column 2
in Table 7) and not the one attempted to be written.
Extended Audio Status/Control Register (Index 2Ah) is ‘set’. If the VRA bit is ‘clear’, all writes
are ignored and the register reads back BB80h; corresponding to a 48 kHz sample rate. If the
VRA bit is ‘set’, seven standard sample rates are available. If a sample rate written to the reg-
ister is not directly supported, the attempted value to be written will be decoded according to
the ranges indicated in Table 7. All register read transactions will reflect the actual value stored
(column 2 in Table 7) and not the one attempted to be written.
Front DAC Sample Rate. The SR[15:0] bits can only be written when the VRA bit of the Extend-
BB80h. This value corresponds to 48 kHz sample rate..
Left/Right ADC Sample Rate. The SR[15:0] bits can only be written when the VRA bit of the
BB80h. This value corresponds to 48 kHz sample rate.
D12
D12
D11
D11
Sample rate
16,000
22,050
32,000
44,100
48,000
11,025
8,000
(Hz)
D10
D10
Table 7. Standard Sample Rates
SR9
SR9
D9
D9
SR[15:0]
SR8
SR8
D8
AC44
BB80
D8
3E80
7D00
1F40
2B11
5622
SR7
SR7
D7
D7
Bh, Ch, Dh, Eh, or Fh
Decode Range
SR6
SR6
D6
D6
SR[15:12]
8, 9, or Ah
0 or 1
4 or 5
6 or 7
2
3
SR5
SR5
D5
D5
SR4
SR4
D4
D4
SR3
SR3
D3
D3
SR2
SR2
D2
D2
CS4299
SR1
SR1
D1
D1
CS4299
SR0
SR0
D0
D0
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