CS4299-JQZ Cirrus Logic Inc, CS4299-JQZ Datasheet - Page 34

• Manufacturer Part Number: CS4299-JQZ
• Description: IC CODEC AC 97 W/SRC 48LQFP
• Manufacturer: Cirrus Logic Inc
• Series: SoundFusion™r
• Type: Audio Codec '97r

Specifications of CS4299-JQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 87
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: AC97
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC/1 DAC
• Supply Current: 10 mA
• Thd Plus Noise: - 74 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1044

5.2
The
(Index 26h) controls the power management func-
tions. The PR[6:0] bits in this register control the
internal powerdown states of the CS4299. Power-
down control is available for individual subsections
of the CS4299 by asserting any PRx bit or any com-
bination of PRx bits. Most powerdown states can
be resumed by clearing the corresponding PRx bit.
Table 11 shows the mapping of the power control
bits to the functions they manage.
When PR0 is ‘set’, the L/R ADCs and the Input
Mux are shut down and the ADC bit in the Power-
down Control/Status Register (Index 26h) is
‘cleared’ indicating the ADCs are no longer in a
ready state. The same is true for the DACs, the an-
alog mixers, and the reference voltage (Vrefout).
When the PR2 or PR3 bit of the mixer is ‘cleared’,
the mixer section will begin a power-on process,
and the corresponding powerdown status bit will be
‘set’ when the hardware is ready.
Shutting down the AC-link by ‘setting’ PR4 causes
the primary Codec to turn off the BIT_CLK and
drive SDATA_IN low. It also ignores SYNC and
34
34
Powerdown Controls
Powerdown
Control/Status
* Applies only to primary codec
PR Bit
PR0
PR1
PR2
PR3
PR4
PR5
PR6
Table 11. Powerdown PR Bit Functions
L/R ADCs and Input Mux Powerdown
Register
Analog Mixer Powerdown (Vref on)
Analog Mixer Powerdown (Vref off)
AC-link Powerdown (BIT_CLK off)*
Alternate Line Out Powerdown
Front DACs Powerdown
Internal Clock Disable
Function
SDATA_OUT in their normal capacities. Either a
Cold Reset or a Warm Reset is required to restore
operation to the CS4299. A Cold Reset will restore
all mixer registers to their power-on default values.
A Warm Reset will not alter the values of any mix-
er register, except clearing the PR4 bit in Power-
down Control/Status Register (Index 26h).
The PR5 bit powers down all analog and digital
subsections of the device. A Cold Reset is the only
way to restore operation to the CS4299 after a PR5
global powerdown.
The CS4299 does not automatically mute any input
or output when the powerdown bits are ‘set’. The
software driver controlling the AC ’97 device must
manage muting the input and output analog signals
before putting the part into any power management
state. The definition of each PRx bit may affect a
single subsection or a combination of subsections
within the CS4299. Table 12 on page 35 contains
the matrix of subsections affected by the respective
PRx function. Table 13 on page 35 shows the dif-
ferent operating power consumptions levels for dif-
ferent powerdown functions.
CS4299
CS4299
DS319PP6