LM4550BVH/NOPB National Semiconductor, LM4550BVH/NOPB Datasheet - Page 26

• Manufacturer Part Number: LM4550BVH/NOPB
• Description: IC AC '97 AUDIO CODEC 48-LQFP
• Manufacturer: National Semiconductor
• Type: Audio Codec '97r

Specifications of LM4550BVH/NOPB

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 89
• Voltage - Supply, Analog: 4.2 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 3
• Adc / Dac Resolution: 18bit
• Sampling Rate: 48kSPS
• Interface Type: Serial
• Supply Voltage Range: 3V To 5.5V, 4.2V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM4550BVH; *LM4550BVH/NOPB; LM4550BVH

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Register Descriptions
dard one SDATA_IN pin per codec. Note, however, that the
chained codecs time-share the bandwidth of the SDATA_IN
signal under allocation from the controller.
The first codec in the chain (nearest the controller) will have
access to the full bandwidth of SDATA_IN following a system
reset (Cold Reset for each codec). To access any other
codec in the chain, the controller must write a suitable value
(i.e. the Identity of the target codec) to the Chain-In Control
register (74h) of each intervening codec in the chain.
The last codec in the serial chain (furthest from the control-
ler) should have its CIN pin connected to digital ground.
When writing software drivers, care should be taken to avoid
any problems that could occur when this last codec in the
chain is set to pass a CIN signal when there is none to pass.
Different controllers may handle an input of all 0s differently
and leaving the CIN pin floating should definitely be avoided.
VENDOR ID REGISTERS (7Ch, 7Eh)
These two read-only (4E53h, 4350h) registers contain Na-
tional’s Vendor ID and National’s LM45xx codec version
designation. The first 24 bits (4Eh, 53h, 43h) represent the
three ASCII characters “NSC” which is National’s Vendor ID
for Microsoft’s Plug and Play. The last 8 bits are the two
binary coded decimal characters, 5, 0 and identify the codec
to be an LM4550 family part.
RESERVED REGISTERS
Do not write to reserved registers. In particular, do not write
to registers 24h, 5Ah and 7Ah. All registers not listed in the
LM4550B Register Map are reserved. Reserved registers
will return 0000h if read.
Low Power Modes
The LM4550B provides 7 bits to control the powerdown state
of internal analog and digital subsections and clocks. It also
provides one bit intended to control an external analog
power amplifier. These 8 bits (PR0 – PR6, EAPD) are the 8
BIT#
1,0
*(bit1,bit0) = (ID1,ID0): Chain-In off
(bit1,bit0) ≠ (ID1,ID0): Chain-In on
Function
(Continued)
FIGURE 8. AC Link Powerdown Timing
26
MSBs of the Powerdown Control/Status register, 26h. The
status of the four main analog subsections is given by the 4
LSBs in the same register, 26h.
The powerdown bits are implemented in compliance with AC
’97 Rev 2.1 to support the standard device power manage-
ment states D0 – D3 as defined in the ACPI and PCI Bus
Power Management specification.
PR0 controls the powerdown state of the ADC and associ-
ated sampling rate conversion circuitry. PR1 controls power-
down for the DAC and the DAC sampling rate conversion
circuitry. PR2 powers down the mixer circuits (MIX1, MIX2,
National 3D Sound, Mono Out, Line Out). PR3 powers down
V
powers down the AC Link Digital Interface – see Figure 8 for
signal powerdown timing. PR5 disables internal clocks but
leaves the crystal oscillator and BIT_CLK running (needed
for minimum Primary mode powerdown dissipation in multi-
codec systems). PR6 powers down the Headphone ampli-
fier. EAPD controls the External Amplifier PowerDown pin
(pin 47).
After a subsection has undergone a powerdown cycle, the
appropriate status bit(s) in the Powerdown Control/Status
register (26h) must be polled to confirm readiness. In par-
ticular the startup time of the V
value of the decoupling capacitors on pin 27 (3.3 µF, 0.1 µF
in parallel is recommended).
When the AC Link Digital Interface is powered down the
codec output signals SDATA_IN and BIT_CLK (Primary
mode) are cleared to zero and no control data can be passed
between controller and codec(s). This powerdown state can
be cleared in two ways: Cold Reset (RESET# = 0) or Warm
Reset (SYNC = 1, no BIT_CLK). Cold Reset sets all regis-
ters back to their default values (including clearing PR4)
whereas Warm Reset only clears the PR4 bit and restarts
the AC Link Digital Interface leaving all register contents
otherwise unaffected. For Warm Reset (see Timing Dia-
grams), the SYNC input is used asynchronously. The
LM4550B codec allows the AC Link digital interface power-
down state to be cleared immediately so that its duration can
essentially be as short as T
However for conformance with AC ’97 Rev 2.1, Warm Reset
should not be applied within 4 frame times of powerdown i.e.
the AC Link powerdown state should be allowed to last at
least 82.8 µs.
REF
in addition to all the same mixer circuits as PR2. PR4
SH
, the Warm Reset pulse width.
REF
circuitry depends on the
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