LM4550BVH/NOPB National Semiconductor, LM4550BVH/NOPB Datasheet
LM4550BVH/NOPB
Specifications of LM4550BVH/NOPB
*LM4550BVH/NOPB
LM4550BVH
Available stocks
Related parts for LM4550BVH/NOPB
LM4550BVH/NOPB Summary of contents
Page 1
... Input Frames (Codec to Controller). Multiple codec systems can be built either using the standard AC Link configuration (i.e. of one serial data signal to the Controller per codec) or using a unique National Semiconductor fea- ture for chaining codecs together. This chain feature shares only a single data signal to the controller among multiple codecs. The AC ’ ...
Page 2
www.national.com 2 ...
Page 3
... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Storage Temperature Input Voltage ESD Susceptibility (Note 2) pin 3 ESD Susceptibility (Note 3) pin 3 Junction Temperature Electrical Characteristics 48 kHz, single codec configuration, unless otherwise noted. Limits apply for T less otherwise specified ...
Page 4
Electrical Characteristics kHz, single codec configuration, unless otherwise noted. Limits apply for T otherwise specified. (Continued) Symbol Parameter Analog to Digital Converters Resolution Dynamic Range (Note 9) Frequency Response Digital to Analog Converters Resolution Dynamic Range (Note 9) THD Total ...
Page 5
Electrical Characteristics kHz, single codec configuration, unless otherwise noted. Limits apply for T otherwise specified. (Continued) Symbol Parameter T Setup Time for codec SYNC input SSETUP T Hold Time for codec SYNC input SHOLD T Output Valid Delay CO T ...
Page 6
Timing Diagrams Clocks Digital Rise and Fall www.national.com Data Delay, Setup and Hold 10097210 10097212 Power On Reset Cold Reset Warm Reset 6 10097211 Legend 10097230 10097229 10097213 10097214 ...
Page 7
Typical Application FIGURE 1. LM4550 Typical Application Circuit, Single Codec, 1 Vrms inputs APPLICATION HINTS • The LM4550 must be initialized by using RESET# to perform a Power On Reset as shown in the Power On Reset Timing Diagram • ...
Page 8
www.national.com 8 ...
Page 9
Connection Diagram Pin Descriptions Name Pin Functional Description Mono Input This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the PC_Beep ...
Page 10
Pin Descriptions (Continued) Name Pin Functional Description Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. ...
Page 11
Pin Descriptions (Continued) Name Pin Functional Description Mono microphone input Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit D8) in the General Purpose register, 20h. The ...
Page 12
Pin Descriptions (Continued) Name Pin Functional Description Left Stereo Channel Output This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal HP_OUT_L 39 O from MIX2 via the Headphone ...
Page 13
Pin Descriptions (Continued) Name Pin Link frame marker and Warm Reset This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In normal operation SYNC kHz positive ...
Page 14
Pin Descriptions (Continued) Name Pin Analog supply Analog ground Digital supply DD1 Digital supply DD2 Digital ground SS1 DV 7 ...
Page 15
Typical Performance Characteristics ADC Frequency Response Line Out Noise Floor (Analog Loopthrough) Headphone Amplifier THD+N vs Frequency (Continued) 10097219 Headphone Amplifier Noise Floor 10097218 10097227 15 DAC Frequency Response 10097220 (Analog Loopthrough) 10097226 Headphone Amplifier THD+N vs Output Power 10097228 ...
Page 16
Volume Output www.national.com Volume Input Sources ADC 16 ...
Page 17
Functional Description GENERAL The LM4550 codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format) inputs and outputs. There are four stereo and four mono analog inputs and two stereo and one mono analog ...
Page 18
AC Link Serial Interface Protocol AC LINK OUTPUT FRAME: SDATA_OUT, CONTROLLER OUTPUT TO LM4550 INPUT The AC Link Output Frame carries control and PCM data to the LM4550 control registers and stereo DAC. Output Frames are carried on the SDATA_OUT ...
Page 19
AC Link Serial Interface Protocol (Continued) data from four slots in a given frame and so only checks the valid-data bits for 4 slots. In Primary mode these tag bits are for: slot 1 (Command Address), slot 2 (Command Data), ...
Page 20
AC Link Serial Interface Protocol (Continued) SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right Channels Slots 3 and 4 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC when the ...
Page 21
AC Link Serial Interface Protocol (Continued) A new Input Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from the controller on a rising edge of BIT_CLK and, as shown in Figure 6 and Figure 7, ...
Page 22
AC Link Serial Interface Protocol (Continued) SLOT 1, INPUT FRAME Bits Description 19 Reserved Stuffed with "0" by LM4550 Status Register Echo of the requested Status 18:12 Index Register address Controller should send Slot 3 Request valid data ...
Page 23
Register Descriptions Default settings are indicated by *. RESET REGISTER (00h) Writing any value to this register causes a Register Reset which changes all registers back to their default values read is performed on this register, the LM4550 ...
Page 24
Register Descriptions Record Gain Register (1Ch) Mute Gx3:Gx0 0 1111 22.5dB gain 0 0000 0dB gain 1 XXXX *mute Default: 8000h GENERAL PURPOSE REGISTER (20h) This register controls many miscellaneous functions imple- mented on the LM4550. The miscellaneous control bits ...
Page 25
Register Descriptions Pin 46 Pin 45 D15,28h D14,28h (ID1#) (ID0#) (ID1) (ID0) NC/DV NC/ NC/DV GND GND NC/ GND GND 1 1 EXTENDED AUDIO STATUS/CONTROL REGISTER (2Ah) This read/write register ...
Page 26
Low Power Modes (Continued) ticular the startup time of the V circuitry depends on the REF value of the decoupling capacitors on pin 27 (3.3 µF, 0.1 µF in parallel is recommended). When the AC Link Digital Interface is powered ...
Page 27
Multiple Codecs (Continued) the controller and any Secondary codecs. Secondary co- decs use BIT_CLK as an input and as their timing source and do not use XTAL_IN or XTAL_OUT, The AMAP map- pings are given in Table 1 and the ...
Page 28
... FIGURE 9. Multiple Codecs using Extended AC Link CODEC CHAINING Using National Semiconductor’s unique feature for chaining together codecs, a multiple codec system can be built using fewer interface pins. This Chain feature allows two, three or four codecs to share a single signal input pin at the control- ler ...
Page 29
Multiple Codecs (Continued) Test Modes AC ’97 Rev 2.1 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit either of them. The ATE test mode is activated if SDATA_OUT is ...
Page 30
... BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. ...