CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 19

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

DS686F1
5. APPLICATIONS
5.1
5.1.1
5.1.2
5.1.3
Stand-Alone Mode
Access to Stand-Alone Mode
Access to Master/Slave Mode
System Clocking
Reliable power-up is achieved by keeping the device in reset until the power supplies, clocks and config-
uration pins are stable. It is also recommended that RST be asserted if the analog or digital supplies drop
below the minimum specified operating voltages to prevent power glitch related issues.
The delay time from the release of reset until the device enters Stand-Alone Mode is 1,045 sample peri-
ods.
The CS4270 supports operation in either Master Mode or Slave Mode.
In Master Mode, LRCK and SCLK are outputs and are synchronously generated by the device. The LRCK
frequency is equal to Fs and the SCLK frequency is equal to 64x Fs.
In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK.
SCLK must be 48x or 64x Fs to maximize system performance.
In Stand-Alone Mode, the CS4270 enters Slave Mode when SDOUT (M/S) is pulled low through a 47 k
resistor. Master Mode is accessed by placing a 47 k pull-up to VD on the SDOUT (M/S) pin.
Configuration of clock ratios in each of these modes is outlined in
The CS4270 operates at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three
speed modes, as shown in
Table 2
Table 2. Approximate Delay Time from Release of RST to Entering Standalone Mode
lists the approximate wait time for each sampling mode.
Single-Speed
Double-Speed
Quad-Speed
Single-Speed
Double-Speed
Quad-Speed
Speed Mode
Table
Mode
3.
Table 3. Speed Modes
Approximate Delay Time
Sampling Frequency
21.8 ms (48 kHz)
10.9 ms (96 kHz)
5.4 ms (192 kHz)
100-216 kHz
50-108 kHz
4-54 kHz
Table
4.
CS4270
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