CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 29

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

DS686F1
6.2
6.2.1
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown
in
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
Software Mode - SPI Control Port
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial clock, CCLK (see
for the clock to data relationship). There are no AD0 or AD1 pins. Pin CS is the chip select signal and is
used to control SPI writes to the registers. When the device detects a high-to-low transition on the AD0/CS
pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the rising edge
of CCLK.
SCL
SDA
SDA
SCL
SPI Write
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
To write to the device, use the following procedure while adhering to the Software Mode switching spec-
ifications in
Figure
START
START
21, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
0
1
0
1
CHIP ADDRESS (WRITE)
CHIP ADDRESS (WRITE)
1
0
“Switching Characteristics - Software Mode - SPI Format” section on page
1
0
0
2
2
0
1
3
1
3
0 AD1 AD0 0
4
1 AD1 AD0 0
4
5
5
6
7
6
ACK
8
7
Figure 20. Software Mode Timing, I²C Write
Figure 21. Software Mode Timing, I²C Read
9
INCR
ACK
8
10 11
6
INCR
9
5
MAP BYTE
10 11
6
12 13 14 15
4
MAP BYTE
5
3
12
4
2
13 14 15
1
3
16
0
2
ACK
STOP
17 18
1
START
16 17 18
0
ACK
19
1
20 21 22 23 24
CHIP ADDRESS (READ)
0
7
0
19
6
DATA
1
0 AD1 AD0 1
24 25
1
0
ACK
25
26
26 27 28
27 28
7
ACK
DATA +1
6
7
DATA
0
1
ACK
0
DATA +1
7
7
18.
DATA +n
0
6
DATA + n
1
7
CS4270
0
Figure 22
ACK
0
ACK
NO
STOP
STOP
29