CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 24

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

24
5.2.8
5.3
5.3.1
5.3.2
5.3.3
5.4
Popguard Transient Control
The CS4270 uses a novel technique to minimize the effects of output transients during power-up and power-
down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended single-supply converters. The Pop-
guard Transient Control is activated inside the DAC when RST is toggled and requires no other external
control, aside from choosing the appropriate DC-blocking capacitor. See
configuration.
De-Emphasis Filter (Single-Speed Mode Only)
Oversampling Modes
Power-Up
Power-Down
Discharge Time
The CS4270 operates in one of three oversampling modes based on the input sample rate. Mode selec-
tion is determined by the FM bits in the Mode Control Register (03h). Single-Speed Mode supports input
sample rates from 4 to 54 kHz and uses a 128x oversampling ratio. Double-Speed Mode supports input
sample rates from 50 to 108 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode supports in-
put sample rates from 100 to 216 kHz and uses an oversampling ratio of 32x. See
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to
AGND.Following a delay of 1,045 sample periods, each output begins to ramp toward the quiescent volt-
age. Approximately 0.4 seconds later, the outputs reach VQ and audio output begins.This gradual voltage
ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing
audible power-up transients.
To prevent audible transients at power-down, the device must first enter its power-down state. When this
occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB.
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis-
charge. Once this charge is dissipated, the power to the device may be turned off and the system is ready
for the next power-on.
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-
fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds.
The CS4270 includes a digital de-emphasis filter.
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in
sample rate, Fs. Please see
Section 5.2
The de-emphasis feature is included to accommodate audio recordings that use 50/15 s pre-emphasis
equalization as a means of noise reduction.
for Serial Control Port Mode.
Section 5.1.7
for the desired de-emphasis control for Stand-Alone Mode and
Figure 14
shows the de-emphasis curve for Fs equal to
Section 8.3.3
Table 7 on page
for information about
CS4270
DS686F1
22.