UDA1355H/N2,557 NXP Semiconductors, UDA1355H/N2,557 Datasheet - Page 61

• Manufacturer Part Number: UDA1355H/N2,557
• Description: IC CODEC STER/SUDIO SPDIF 44QFP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1355H/N2,557

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 98
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935271552557

NXP Semiconductors
Table 78 Description of register bits (address 18H)
12.3.2
Table 79 Register address 28H
Table 80 Description of register bits (address 28H)
2003 Apr 10
Symbol
Symbol
15 to 7 −
15 to 3 −
Stereo audio codec with SPDIF interface
BIT
BIT
BIT
BIT
6
5
4
3
2
1
0
2
1
0
D
SDETR2
SDETL2
SDETR1
SDETL1
MUTE_STATE_M
MUTE_STATE_CH2
MUTE_STATE_CH1
ECIMATOR
MT_ADC_stat
−
OVERFLOW
SYMBOL
15
−
7
−
SYMBOL
14
reserved
Mute status decimator. If this bit is logic 0 then the decimator is not muted; if this bit is
logic 1 then the decimator is muted.
reserved
Overflow decimator. If this bit is logic 0 then there is no overflow in the decimator (digital
level above −1.16 dB.); if this bit is logic 1 then there is an overflow in the decimator.
−
6
−
reserved
Silence detector channel 2 right. If this bit is logic 0 then there is no silence
detection for the right input of channel 2; if this bit is logic 1 then there is silence
detection for the right input of channel 2.
Silence detector channel 2 left. If this bit is logic 0 then there is no silence
detection for the left input of channel 2; if this bit is logic 1 then there is silence
detection for the left input of channel 2.
Silence detector channel 1 right. If this bit is logic 0 then there is no silence
detection for the right input of channel 1; if this bit is logic 1 then there is silence
detection for the right input of channel 1.
Silence detector channel 1 left. If this bit is logic 0 then there is no silence
detection for the left input of channel 1; if this bit is logic 1 then there is silence
detection for the left input of channel 1.
Mute status interpolator. If this bit is logic 0 then the interpolator is not muted; if this
bit is logic 1 then the interpolator is muted.
Mute status channel 2. If this bit is logic 0 then the interpolator channel 2 is not
muted; if this bit is logic 1 then the interpolator channel 2 is muted.
Mute status channel 1. If this bit is logic 0 then the interpolator channel 1 is not
muted; if this bit is logic 1 then the interpolator channel 1 is muted.
13
−
5
−
12
−
4
−
61
DESCRIPTION
11
−
3
−
DESCRIPTION
MT_ADC_stat
10
−
2
Preliminary specification
9
−
1
−
UDA1355H
OVERFLOW
8
−
0