UDA1355H/N2,518 NXP Semiconductors, UDA1355H/N2,518 Datasheet
UDA1355H/N2,518
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UDA1355H/N2,518 Summary of contents
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DATA SHEET UDA1355H Stereo audio codec with SPDIF interface Preliminary specification INTEGRATED CIRCUITS 2003 Apr 10 ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface CONTENTS 1 FEATURES 1.1 General 1.2 Control 1.3 IEC 60958 input 1.4 IEC 60958 output 1.5 Digital I/O interface 1.6 ADC digital sound processing 1.7 DAC digital sound processing 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 1 FEATURES 1.1 General • 2.7 to 3.6 V power supply • Integrated digital interpolator filter and Digital-to-Analog Converter (DAC) • 24-bit data path in interpolator • No analog post filtering required for DAC • Integrated Analog-to-Digital Converter (ADC), ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface • Programmable digital silence detector • Interpolating filter (f to 64f recursive and a FIR filter in cascade • Selectable fifth-order noise shaper operating at 64f third-order noise shaper operating at 128f low sampling frequencies, e.g. 16 kHz) generating bitstream for DAC • ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 4 QUICK REFERENCE DATA SYMBOL PARAMETER Supplies V DAC supply voltage DDA1 V ADC supply voltage DDA2 V crystal oscillator and PLL DDX supply voltage V digital core supply voltage DDI V digital pad supply voltage DDE I DAC supply current ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface SYMBOL PARAMETER Analog-to-digital converter (rms) input voltage (RMS value) i ΔV input voltage unbalance i (THD+N)/S total harmonic distortion-plus-noise to signal ratio S/N signal-to-noise ratio α channel separation cs External crystal f crystal frequency xtal C crystal load capacitor ...
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V DDX V SSX V ADCP V DDA2 CLK_OUT XTALIN CLOCK AND XTAL 14 TIMING XTALOUT 34 VINL ADC COMB DECI- FILTER MATOR 36 PROCESSOR VINR ADC 16 RESET 43 RTCB 2 WSI 3 ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 6 PINNING SYMBOL PIN PAD BCKI 1 bpt4mtht5v WSI 2 bpt4mtht5v DATAI 3 iptht5v LOCK 4 op4mc SPDIFOUT 5 op4mc V 6 vdde DDE V 7 vsse SSE DATAO 8 ops5c WSO 9 bpt4mtht5v BCKO 10 bpt4mtht5v CLK_OUT 11 op4mc V 12 vddco DDX XTALIN 13 apio ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface SYMBOL PIN PAD VINL 34 apio V 35 vssco SSA2 VINR 36 apio V 37 vddco DDA2 V 38 apio REF V 39 vddco DDA1 VOUTL 40 apio V 41 vssco SSA1 VOUTR 42 apio RTCB 43 ipthdt5v MUTE 44 iipthdt5v Note 1. See Table 1. ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface handbook, full pagewidth BCKI WSI DATAI LOCK SPDIFOUT V DDE V SSE DATAO WSO BCKO CLK_OUT 7 FUNCTIONAL DESCRIPTION 7.1 IC control The UDA1355H can be controlled either via static pins or via the microcontroller serial hardware interface being the ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface • Set two times 40 bits of channel status bits of the SPDIF output • Select one of four SPDIF input sources • Enable digital mixer inside interpolator • Control mute and mixer volumes of digital mixer • Selection of filter mode and settings of treble and bass boost for the interpolator (DAC) section • ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 12.288 MHz handbook, halfpage 13 XTALIN CRYSTAL 14 OSCILLATOR XTALOUT 256f s or 384f s clock 11 CLK_OUT PLL clock 2 L3-bus or I C-bus register setting Fig.3 Crystal oscillator clock system. 7.3.2 PLL CLOCK SYSTEM The PLL locks on the incoming digital data of the SPDIF or WS input signal ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 7.4.2 C HANNEL STATUS AND USER BITS As well as the data bits there are several IEC 60958 key channel status bits: • Pre-emphasis and audio sampling frequency bits • Two channel PCM indicator bits • Clock accuracy bits. ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface handbook, full pagewidth SPDOUT_SEL1 23 SPDIF0 24 SPDIF1 25 SPDIF2 26 SPDIF3 SLICER_SEL [ 1:0 ] 7.6 Analog input 7.6.1 ADC The analog input is equipped with a Programmable Gain Amplifier (PGA) which can be controlled via the microcontroller interface. The control range is from gain steps independent for the left and right channels ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 7.6.3 DC FILTERING In the decimator there are two digital DC blocking circuits. The first blocking circuit is in front of the volume control to remove DC bias from the ADC output. The DC bias is added in the ADC to prevent audio band Idle tones occurring in the noise shaper ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 7 Interpolation filter characteristics ITEM CONDITIONS Pass-band ripple 0 to 0.45f Stop band >0.55f Dynamic range 0 to 0.4535f 7.7.3 D IGITAL MIXER The UDA1355H has a digital mixer inside the interpolator. The digital mixer can be used as a cross over or a selector. ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface handbook, full pagewidth channel 2 VOLUME DE-EMPHASIS AND MUTE VOLUME DE-EMPHASIS AND MUTE channel 1 7.7.4 D IGITAL SILENCE DETECTOR The UDA1355H is equipped with a digital silence detector. This detects whether a certain amount of consecutive samples are 0. The number of samples can be set with bits SD_VALUE[1:0] to 3200, 4800, 9600 or 19600 samples ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 8 Muting to prevent plopping OCCASION Input selection Select channel 1 source Select channel 2 source Select chip mode PLL is source for the DAC Crystal is source for the DAC Select between microcontroller mode and static mode ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface handbook, halfpage Transmission gate for 5V tolerance 16 RESET V SS UDA1355H Fig. tolerant pull-down input pad. The clock should be running during the reset time. When no clock can be guaranteed in microcontroller mode, a soft reset should be given when the system is running by writing to register 7FH ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface STATIC MODE PIN SYMBOL 30, 31 SFOR1, SFOR0 44 MUTE Note 1. FPLL 256fs is output from pin CLKOUT in PLL locked static mode. 8.2 Static mode basic applications The static application modes are selected with the pins MODE2, MODE1 and MODE0, with pin MODE0 being a 3-level pin ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface The first 11 application modes are given in this section. Schematic diagrams of these application modes are given in Table 11. In this table the basic features are mentioned and also the extra features in case of microcontroller mode are given ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface MODE FEATURES 2 Data path: • Input SPDIF to outputs I SPDIFOUT via loop through • Input output DAC. Features: • Possibility to process input SPDIF via 2 I S-bus using an external DSP and then to output DAC • System locks onto the SPDIF input signal • ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface MODE FEATURES 5 Data path: • Input ADC to outputs I • Input output DAC. Features: • Possibility to process input ADC via 2 I S-bus using an external DSP and then to output DAC • Crystal oscillator generates the clocks • ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface MODE FEATURES 7 Data path: • Input SPDIF to output DAC • Input ADC to outputs SPDIF or I Features: • Crystal oscillator generates the clocks for outputs SPDIF and I • PLL locks onto the SPDIF input signal • ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface MODE FEATURES 9 Data path: • Input SPDIF to output I • Input outputs DAC or SPDIF. Features: • Possibility to process input SPDIF, via 2 I S-bus using an external DSP and then to outputs DAC or SPDIF • BCK and WS being master for both I input and output (different clocks) • ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 8.3 Microcontroller mode pin assignment In microcontroller mode all features become available, such as volume control, PGA gain and mixing (in some modes). The pin functions are defined in Table 12. Table 12 Microcontroller mode pin assignment SYMBOL SYMBOL ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 8.4 Microcontroller mode applications In Table 13, the encoding of bits MODE[3:0] in the microcontroller mode is given. Table 13 Microcontroller mode applications MODE BITS MODE MODE[3:0] 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface In the microcontroller mode, more features are available. The application modes are given in Table 14. Some modes are the same in terms of data path as for the static mode. These modes are already explained in Section 8.2. Some modes are combined into one mode (like modes 4 and 5) ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface MODE FEATURE 6 See static mode 7 See static mode 8 See static mode 9 Data path: • Inputs ADC and outputs DAC or SPDIF • Input SPDIF to output I Features: • Input SPDIF to output I and WS being master; the clocks for ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface MODE FEATURE 12 Data path: • Input ADC to outputs I • Inputs and SPDIF to output DAC. Features: • BCK and output are master • Inputs SPDIF and I 2 with mixing/selection possibility; clocks are generated from SPDIF input signal, and BCK and WS are master • ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 9 SPDIF SIGNAL FORMAT 9.1 SPDIF channel encoding The digital signal is coded using Biphase Mark Code (BMC), which is a kind of phase modulation. In this scheme, a logic 1 in the data corresponds to two zero-crossings in the coded signal, and a logic 0 to one zero-crossing ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 15 Preambles CHANNEL CODING PRECEDING STATE 0 B 11101000 M 11100010 W 11100100 9.3 Timing characteristics 9.3.1 F REQUENCY REQUIREMENTS The SPDIF specification IEC 60958 supports three levels of clock accuracy: • Level I high accuracy: Tolerance of transmitting sampling frequency shall be within 50 × 10 • ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 16 Selection of data transfer DOM BITS BIT 0 BIT not used 1 0 not used 0 1 write data or prepare read 1 1 read data The device address of the UDA1355H is given in Table 17, being the first 6 bits of the device address byte. The address can be set one of two by using pin MODE1 (pin A0 in microcontroller mode) ...
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L3 wake-up pulse after power-up L3CLOCK L3MODE device address 0 1 L3DATA DOM bits L3CLOCK L3MODE device address register address L3DATA DOM bits read prepare read register address data byte 1 0 write Fig.15 Data write mode. ...
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... For a 400 kHz IC the recommendation for this type of bus from NXP Semiconductors must be followed (e. loads of 200 pF on the bus a pull-up resistor can be used, between 200 to 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 11.3 Byte transfer Each byte (8 bits) is transferred with the MSB first (see Table 20). Table 20 Byte transfer MSB BIT 11.4 Data transfer A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface handbook, full pagewidth DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER 11.9 Write cycle The write cycle is used to write groups of two bytes to the internal registers for the digital sound feature control and system setting ...
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Read cycle The read cycle is used to read the data values from the internal registers. The I The format of the read cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 12 REGISTER MAPPING In this chapter the register addressing of the microcontroller interface of the UDA1355H is given. In Section 12.1, the mapping of the readable and writable registers is given. The explanation of the register definitions are explained in Sections 12.2 and 12.3. ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface ADDRESS R/W 5DH R SPDIF input status bits right channel read-out 5EH R SPDIF input status bits right channel read-out 5FH R SPDIF input status bits right channel read-out SPDIF output 50H R/W SPDIF output valid; left to right channel status bit copy; power control and SPDIF output ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 26 Description of register bits (address 00H) BIT SYMBOL 15 EXPU − PON_XTALPLL XTL_DIV[4: MODE[3:0] 3 ws_detct_EN 2 ws_detct_set 1 and 0 CLKOUT_SEL[1:0] Clock output select. If these bits are 00 or 10, then the BCKI and BCKO clock Table 27 Crystal oscillator output frequencies ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface XTL_DIV4 XTL_DIV3 Based on 48 kHz Table 28 Application mode selection MODE3 MODE2 Table 29 Register address 01H BIT 15 14 − − Symbol Default 0 0 BIT 7 6 − Symbol PON_DIGO Default 1 0 2003 Apr 10 XTL_DIV2 XTL_DIV1 ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 30 Description of register bits (address 01H) BIT SYMBOL − reserved 8 MUTE_DAO Digital mute setting. If this bit is logic 0, then the digital output is not muted; if this bit is logic 1, then the digital output is muted. 7 PON_DIGO Power control digital output. If this bit is logic 0, then the digital output is in Power-down mode ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface BIT SYMBOL SFORI[2:0] Digital input format. Value to set the digital input format: 000 = I 001 = LSB-justified; 16 bits 010 = LSB-justified; 18 bits 011 = LSB-justified; 20 bits 100 = LSB-justified; 24 bits 101 = MSB-justified 110 = not used; input is default value 111 = not used ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 35 ADC power control PON_ADC_BIAS PON_ADCR 12.2.2 I NTERPOLATOR Table 36 Register address 10H BIT 15 14 Symbol MVCL_7 MVCL_6 Default 0 BIT 7 Symbol MVCR_7 MVCR_6 Default 0 Table 37 Description of register bits (address 10H) BIT SYMBOL MVCL_[7:0] Master volume setting left channel. Value to program the left channel master volume attenuation. The range − ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface MVCL_7 MVCL_6 MVCL_5 MVCR_7 MVCR_6 MVCR_5 Table 39 Register address 11H BIT 15 14 Symbol VC2_7 VC2_6 Default 1 1 BIT 7 6 Symbol VC1_7 VC1_6 Default 0 0 Table 40 Description of register bits (address 11H) BIT SYMBOL VC2_[7:0] Mixer volume setting channel 2. Value to program channel 2 mixer volume attenuation. The range − ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface VC2_7 VC2_6 VC2_5 VC2_4 VC1_7 VC1_6 VC1_5 VC1_4 Table 42 Register address 12H BIT 15 Symbol M1 Default 0 BIT 7 Symbol BB_OFF BB_FIX Default 0 Table 43 Description of register bits (address 12H) BIT SYMBOL 15 and 14 M[1:0] Sound feature mode. Value to program the sound processing filter sets (modes) of bass ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface BIT SYMBOL 6 BB_FIX Resonant bass boost coefficient. If this bit is logic 0 then the resonant bass boost coefficient is finished loading; if this bit is logic 1 then the resonant bass boost coefficient is loading to register. 5 and 4 TRR[1:0] Treble settings right. Value to program the right treble setting. The used filter set is selected by the sound feature mode bits M1 and M2 (see Table 44) ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 46 Register address 13H BIT 15 − Symbol Default 0 BIT 7 Symbol MTNS1 MTNS0 Default 0 Table 47 Description of register bits (address 13H) BIT SYMBOL 15 - reserved 14 MTM Master mute. If this bit is logic 0 then there is no master mute or the master de-mute is in progress ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 49 Mixer gain setting (1) MIX MIX_GAIN 1 1 Note 1. See Table 52. Table 50 De-emphasis setting for the incoming signal DE2_2 DE2_1 DE1_2 DE1_1 Table 51 Register address 14H BIT 15 14 Symbol DA_POL_ SEL_NS INV Default 0 1 BIT ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface BIT SYMBOL 7 SILENCE 6 SDET_ON 5 and 4 SD_VALUE[1:0] 3 BASS_SEL 2 BYPASS 1 and 0 OS_IN[1:0] Table 53 Mixer signal control signals MIX MIX_POS ( Note don’t care 2003 Apr 10 Silence detector overrule. Value to force the DAC output to silence. This will give a plop at the output of the DAC because of mismatch in offsets and the DC offset added to the signal in the interpolator itself ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 54 Data source selector DAC channel 1 and 2; note 1 DAC_CH2_SEL1 DAC_CH2_SEL0 DAC_CH1_SEL1 DAC_CH1_SEL0 Note 1. The change of the data source will take place only when the mix mode is turned on (bit MIX = 1). The channel 2 input selection is valid only when the channel 1 data source is correct. ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 58 Description of register bits (address 20H) BIT SYMBOL MA_DECL[7:0] ADC volume setting left channel. Value to program the ADC gain setting for the left channel. The range is from +24 to −63 dB and −∞ dB (see Table 59). ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 61 Description of register bits (address 21H) BIT SYMBOL 15 MT_ADC − PGA_GAIN_CTRLL[3:0] − PGA_GAIN_CTRLR[3:0] Table 62 ADC input amp PGA gain settings PGA_GAIN_ PGA_GAIN_ CTRLL3 CTRLL2 PGA_GAIN_ PGA_GAIN_ CTRLR3 CTRLR2 Table 63 Register address 22H BIT ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface BIT SYMBOL − reserved 1 DC_SKIP DC filter skip. If this bit is logic 0 then the DC filter is enabled; if this bit is logic 1 then the DC filter is disabled. The DC filter is at the output of the comb filter just before the decimator. This DC filter compensates for the DC offset added in the ADC (to remove idle tones from the audio band) ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 12.2.5 SPDIF OUTPUT SETTINGS Table 67 Register address 50H BIT 15 14 − − Symbol Default 0 0 BIT 7 6 − Symbol L_r_copy Default 0 1 Table 68 Description of register bits (address 50H) BIT SYMBOL − 8 SPDO_VALID − ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 69 Register addresses 51H (left) and 54H (right) BIT 15 Symbol SPDO_ SPDO_ BIT39 Default 0 BIT 7 Symbol SPDO_ SPDO_ BIT31 Default 0 Table 70 Register addresses 52H (left) and 55H (right) BIT 15 Symbol SPDO_ SPDO_ BIT23 ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface BIT SYMBOL SPDO_BIT[29:28 SPDO_BIT[27:24 SPDO_BIT[23:20 SPDO_BIT[19:16 SPDO_BIT[15: SPDO_BIT[7: SPDO_BIT[5:3] 2 SPDO_BIT2 1 SPDO_BIT1 0 SPDO_BIT0 Table 73 Word length SPDO_BIT32 SPDO_BIT35 2003 Apr 10 Clock accuracy. Value indicating the clock accuracy level level level III 11 = reserved Sample frequency. Value indicating the sampling frequency: 0000 = 44 ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface SPDO_BIT32 SPDO_BIT35 Table 74 Channel number SPDO_BIT23 SPDO_BIT22 Table 75 Source number SPDO_BIT19 SPDO_BIT18 2003 Apr 10 SPDO_BIT34 SPDO_BIT33 SPDO_BIT21 SPDO_BIT20 SPDO_BIT17 SPDO_BIT16 Preliminary specification UDA1355H WORD LENGTH indicated 20 bits 22 bits reserved 23 bits 24 bits 21 bits reserved CHANNEL NUMBER don’ ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface SPDO_BIT19 SPDO_BIT18 Table 76 General information SPDO_BIT[15:8] 00000 000 Lxxxx 001 Lxxxx 010 Lxxxx 011 Lxxxx 100 Lxxxx 110 Lxxxx 101 Lxx00 110 Lxx10 110 Lxxx1 000 L1000 000 Lxxxx 111 Lxxx0 000 12.3 Read registers mapping 12 ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 78 Description of register bits (address 18H) BIT SYMBOL − 6 SDETR2 5 SDETL2 4 SDETR1 3 SDETL1 2 MUTE_STATE_M 1 MUTE_STATE_CH2 0 MUTE_STATE_CH1 12.3.2 D ECIMATOR Table 79 Register address 28H BIT 15 14 − − Symbol BIT 7 6 − − Symbol Table 80 Description of register bits (address 28H) ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 12.3.3 SPDIF INPUT Table 81 Register address 59H BIT 15 14 − − Symbol BIT 7 6 − − Symbol Table 82 Description of register bits (address 59H) BIT SYMBOL − reserved 8 SPDO_STATUS SPDIF encoder output status. If this bit is logic 0 then the SPDIF encoder output is enabled ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface Table 85 register address 5AH (left) and 5DH (right); see note 1 BIT 15 Symbol SPDI_ SPDI_ BIT15 BIT 7 Symbol SPDI_ SPDI_ BIT7 Note 1. See for the description of the SPDI bit the corresponding SPDO bit description of Table 72. ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 15 CHARACTERISTICS = 25 ° 3 kΩ; all voltages referenced to ground; unless otherwise specified; note 1. DD amb L SYMBOL PARAMETER Supplies V DAC supply voltage DDA1 V ADC supply voltage DDA2 V crystal oscillator and PLL DDX supply voltage V digital core supply voltage ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface SYMBOL PARAMETER Reference voltage V reference voltage on REF pin REF Digital-to-analog converter V output voltage (RMS value) o(rms) ΔV output voltage unbalance o (THD+N)/S total harmonic distortion-plus-noise to signal ratio S/N signal-to-noise ratio α channel separation cs R load resistance ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface SYMBOL PARAMETER IEC 60958 inputs V input voltage (peak-to-peak i(p-p) value) R input resistance i V hysteresis voltage hys DD(diff) DD(DAC,input) DD(DAC,no input) Power consumption P total power consumption tot Notes 1. All power supply pins (V and When the DAC must drive a higher capacitive load (above 50 pF), then a series resistor of 100 Ω ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface SYMBOL PARAMETER L3-bus interface (see Figs 21 and 22) t rise time r t fall time f T L3CLOCK cycle time cy(CLK)L3 t L3CLOCK HIGH time CLK(L3)H t L3CLOCK LOW time CLK(L3)L t L3MODE set-up time in su(L3)A address mode t L3MODE hold time in ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface SYMBOL PARAMETER t data hold time HD;DAT t pulse width of spikes SP C load capacitance L Notes 1. In order to prevent digital noise interfering with the L3-bus communication, the rise and fall times should be as small as possible. 2. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to 3 ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface handbook, full pagewidth L3MODE t h(L3)A L3CLOCK L3DATA handbook, full pagewidth t stp(L3) L3MODE t su(L3)D L3CLOCK L3DATA write L3DATA read Fig.22 L3-bus interface timing for data transfer mode (write and read). 2003 Apr 10 t CLK(L3)L ...
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SDA t BUF t LOW t r SCL t HD;STA t HD;DAT HD;STA t SU;STA t HIGH t SU;DAT Sr 2 Fig.23 I C-bus interface timing SU;STO P MBC611 ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 17 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1. pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.25 1.85 mm 2.1 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors Stereo audio codec with SPDIF interface 18 SOLDERING 18.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). ...
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... Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your NXP Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “ ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. ...